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authorMatthias P. Braendli <matthias.braendli@mpb.li>2021-03-20 11:45:23 +0100
committerMatthias P. Braendli <matthias.braendli@mpb.li>2021-03-20 11:45:23 +0100
commit2071c8485241e0b95de891e8855542d7c51915ab (patch)
tree77a634e97775b3552705855a60f6b4eadc7de2ac
parent336048a49af662684a76871a4974f8fb93239b99 (diff)
downloadpicardy-2071c8485241e0b95de891e8855542d7c51915ab.tar.gz
picardy-2071c8485241e0b95de891e8855542d7c51915ab.tar.bz2
picardy-2071c8485241e0b95de891e8855542d7c51915ab.zip
Create eval-clock-cw-tx sw
-rw-r--r--sw/eval-clock-cw-tx/.cargo/config8
-rw-r--r--sw/eval-clock-cw-tx/.gdbinit18
-rw-r--r--sw/eval-clock-cw-tx/Cargo.lock359
-rw-r--r--sw/eval-clock-cw-tx/Cargo.toml33
-rw-r--r--sw/eval-clock-cw-tx/Makefile18
-rw-r--r--sw/eval-clock-cw-tx/README.md24
-rw-r--r--sw/eval-clock-cw-tx/build.rs16
-rw-r--r--sw/eval-clock-cw-tx/memory.x6
-rw-r--r--sw/eval-clock-cw-tx/src/cw.rs200
-rw-r--r--sw/eval-clock-cw-tx/src/log10f.rs91
-rw-r--r--sw/eval-clock-cw-tx/src/main.rs367
-rw-r--r--sw/eval-clock-cw-tx/src/si_clock.rs132
-rw-r--r--sw/eval-clock-cw-tx/src/state.rs83
-rw-r--r--sw/eval-clock-cw-tx/src/ui.rs274
-rw-r--r--sw/eval-clock-cw-tx/utils/STM32H7x3.svd101939
-rw-r--r--sw/eval-clock-cw-tx/utils/debug.gdb15
-rw-r--r--sw/eval-clock-cw-tx/utils/stm32h7x3i.cfg141
17 files changed, 103724 insertions, 0 deletions
diff --git a/sw/eval-clock-cw-tx/.cargo/config b/sw/eval-clock-cw-tx/.cargo/config
new file mode 100644
index 0000000..34ba36c
--- /dev/null
+++ b/sw/eval-clock-cw-tx/.cargo/config
@@ -0,0 +1,8 @@
+[target.thumbv7m-none-eabi]
+runner = 'arm-none-eabi-gdb'
+rustflags = [
+ "-C", "link-arg=-Tlink.x",
+]
+
+[build]
+target = "thumbv7m-none-eabi"
diff --git a/sw/eval-clock-cw-tx/.gdbinit b/sw/eval-clock-cw-tx/.gdbinit
new file mode 100644
index 0000000..08b6398
--- /dev/null
+++ b/sw/eval-clock-cw-tx/.gdbinit
@@ -0,0 +1,18 @@
+target remote :3333
+
+monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.fifo uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
+#load
+#step
diff --git a/sw/eval-clock-cw-tx/Cargo.lock b/sw/eval-clock-cw-tx/Cargo.lock
new file mode 100644
index 0000000..8007053
--- /dev/null
+++ b/sw/eval-clock-cw-tx/Cargo.lock
@@ -0,0 +1,359 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+[[package]]
+name = "aligned"
+version = "0.3.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c19796bd8d477f1a9d4ac2465b464a8b1359474f06a96bb3cda650b4fca309bf"
+dependencies = [
+ "as-slice",
+]
+
+[[package]]
+name = "arrayvec"
+version = "0.5.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "23b62fc65de8e4e7f52534fb52b0f3ed04746ae267519eef2a83941e8085068b"
+
+[[package]]
+name = "as-slice"
+version = "0.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "45403b49e3954a4b8428a0ac21a4b7afadccf92bfd96273f1a58cd4812496ae0"
+dependencies = [
+ "generic-array 0.12.4",
+ "generic-array 0.13.3",
+ "generic-array 0.14.4",
+ "stable_deref_trait",
+]
+
+[[package]]
+name = "bare-metal"
+version = "0.2.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5deb64efa5bd81e31fcd1938615a6d98c82eafcbcd787162b6f63b91d6bac5b3"
+dependencies = [
+ "rustc_version",
+]
+
+[[package]]
+name = "bitfield"
+version = "0.13.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "46afbd2983a5d5a7bd740ccb198caf5b82f45c40c09c0eed36052d91cb92e719"
+
+[[package]]
+name = "bitflags"
+version = "1.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cf1de2fe8c75bc145a2f577add951f8134889b4795d47466a54a5c846d691693"
+
+[[package]]
+name = "cast"
+version = "0.2.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "4b9434b9a5aa1450faa3f9cb14ea0e8c53bb5d2b3c1bfd1ab4fc03e9f33fbfb0"
+dependencies = [
+ "rustc_version",
+]
+
+[[package]]
+name = "cortex-m"
+version = "0.6.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9075300b07c6a56263b9b582c214d0ff037b00d45ec9fde1cc711490c56f1bb9"
+dependencies = [
+ "aligned",
+ "bare-metal",
+ "bitfield",
+ "cortex-m 0.7.2",
+ "volatile-register",
+]
+
+[[package]]
+name = "cortex-m"
+version = "0.7.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "643a210c1bdc23d0db511e2a576082f4ff4dcae9d0c37f50b431b8f8439d6d6b"
+dependencies = [
+ "bare-metal",
+ "bitfield",
+ "embedded-hal",
+ "volatile-register",
+]
+
+[[package]]
+name = "cortex-m-rt"
+version = "0.6.13"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "980c9d0233a909f355ed297ef122f257942de5e0a2cb1c39f60684b65bcb90fb"
+dependencies = [
+ "cortex-m-rt-macros",
+ "r0",
+]
+
+[[package]]
+name = "cortex-m-rt-macros"
+version = "0.1.8"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "4717562afbba06e760d34451919f5c3bf3ac15c7bb897e8b04862a7428378647"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "cortex-m-semihosting"
+version = "0.3.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6bffa6c1454368a6aa4811ae60964c38e6996d397ff8095a8b9211b1c1f749bc"
+dependencies = [
+ "cortex-m 0.7.2",
+]
+
+[[package]]
+name = "embedded-dma"
+version = "0.1.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "46c8c02e4347a0267ca60813c952017f4c5948c232474c6010a381a337f1bda4"
+dependencies = [
+ "stable_deref_trait",
+]
+
+[[package]]
+name = "embedded-hal"
+version = "0.2.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb"
+dependencies = [
+ "nb 0.1.3",
+ "void",
+]
+
+[[package]]
+name = "eval_clock_cw_tx"
+version = "0.1.0"
+dependencies = [
+ "arrayvec",
+ "cortex-m 0.6.7",
+ "cortex-m-rt",
+ "cortex-m-semihosting",
+ "embedded-hal",
+ "hd44780-driver",
+ "nb 1.0.0",
+ "panic-semihosting",
+ "shared-bus",
+ "si5351",
+ "stm32f1xx-hal",
+]
+
+[[package]]
+name = "generic-array"
+version = "0.12.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ffdf9f34f1447443d37393cc6c2b8313aebddcd96906caf34e54c68d8e57d7bd"
+dependencies = [
+ "typenum",
+]
+
+[[package]]
+name = "generic-array"
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f797e67af32588215eaaab8327027ee8e71b9dd0b2b26996aedf20c030fce309"
+dependencies = [
+ "typenum",
+]
+
+[[package]]
+name = "generic-array"
+version = "0.14.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "501466ecc8a30d1d3b7fc9229b122b2ce8ed6e9d9223f1138d4babb253e51817"
+dependencies = [
+ "typenum",
+ "version_check",
+]
+
+[[package]]
+name = "hd44780-driver"
+version = "0.3.0"
+dependencies = [
+ "embedded-hal",
+]
+
+[[package]]
+name = "nb"
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f"
+dependencies = [
+ "nb 1.0.0",
+]
+
+[[package]]
+name = "nb"
+version = "1.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae"
+
+[[package]]
+name = "panic-semihosting"
+version = "0.5.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c3d55dedd501dfd02514646e0af4d7016ce36bc12ae177ef52056989966a1eec"
+dependencies = [
+ "cortex-m 0.7.2",
+ "cortex-m-semihosting",
+]
+
+[[package]]
+name = "proc-macro2"
+version = "1.0.24"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1e0704ee1a7e00d7bb417d0770ea303c1bccbabf0ef1667dae92b5967f5f8a71"
+dependencies = [
+ "unicode-xid",
+]
+
+[[package]]
+name = "quote"
+version = "1.0.9"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "c3d0b9745dc2debf507c8422de05d7226cc1f0644216dfdfead988f9b1ab32a7"
+dependencies = [
+ "proc-macro2",
+]
+
+[[package]]
+name = "r0"
+version = "0.2.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
+
+[[package]]
+name = "rustc_version"
+version = "0.2.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a"
+dependencies = [
+ "semver",
+]
+
+[[package]]
+name = "semver"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403"
+dependencies = [
+ "semver-parser",
+]
+
+[[package]]
+name = "semver-parser"
+version = "0.7.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3"
+
+[[package]]
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+dependencies = [
+ "cortex-m 0.6.7",
+ "embedded-hal",
+]
+
+[[package]]
+name = "si5351"
+version = "0.2.0"
+dependencies = [
+ "bitflags",
+ "embedded-hal",
+]
+
+[[package]]
+name = "stable_deref_trait"
+version = "1.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3"
+
+[[package]]
+name = "stm32f1"
+version = "0.11.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "849b1e8d9bcfd792c9d9178cf86165d299a661c26e35d9322ae9382d3f3fe460"
+dependencies = [
+ "bare-metal",
+ "cortex-m 0.6.7",
+ "cortex-m-rt",
+ "vcell",
+]
+
+[[package]]
+name = "stm32f1xx-hal"
+version = "0.7.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bf679de34580d2f8806d9a6384c110b6df002404e1ff024cf8d567c91df4d4b2"
+dependencies = [
+ "cast",
+ "cortex-m 0.6.7",
+ "cortex-m-rt",
+ "embedded-dma",
+ "embedded-hal",
+ "nb 0.1.3",
+ "stm32f1",
+ "void",
+]
+
+[[package]]
+name = "syn"
+version = "1.0.64"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3fd9d1e9976102a03c542daa2eff1b43f9d72306342f3f8b3ed5fb8908195d6f"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "unicode-xid",
+]
+
+[[package]]
+name = "typenum"
+version = "1.13.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "879f6906492a7cd215bfa4cf595b600146ccfac0c79bcbd1f3000162af5e8b06"
+
+[[package]]
+name = "unicode-xid"
+version = "0.2.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f7fe0bb3479651439c9112f72b6c505038574c9fbb575ed1bf3b797fa39dd564"
+
+[[package]]
+name = "vcell"
+version = "0.1.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
+
+[[package]]
+name = "version_check"
+version = "0.9.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5fecdca9a5291cc2b8dcf7dc02453fee791a280f3743cb0905f8822ae463b3fe"
+
+[[package]]
+name = "void"
+version = "1.0.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
+
+[[package]]
+name = "volatile-register"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0d67cb4616d99b940db1d6bd28844ff97108b498a6ca850e5b6191a532063286"
+dependencies = [
+ "vcell",
+]
diff --git a/sw/eval-clock-cw-tx/Cargo.toml b/sw/eval-clock-cw-tx/Cargo.toml
new file mode 100644
index 0000000..b56ac96
--- /dev/null
+++ b/sw/eval-clock-cw-tx/Cargo.toml
@@ -0,0 +1,33 @@
+[package]
+name = "eval_clock_cw_tx"
+version = "0.1.0"
+authors = ["Matthias P. Braendli <matthias.braendli@mpb.li>"]
+edition = "2018"
+license = "MIT"
+
+[dependencies]
+arrayvec = { version = "0.5", default-features = false, features = [] }
+# alloc-cortex-m = "0.3" # requires nightly
+cortex-m = "0.6"
+cortex-m-rt = "0.6"
+# consider cortex-m-rtfm
+cortex-m-semihosting = "0.3"
+panic-semihosting = "0.5"
+nb = "1.0"
+#stm32h7 = { version = "0.9", features = ["stm32h743", "rt"] }
+stm32f1xx-hal = { version = "0.7", features = ["rt", "stm32f103", "medium"] }
+embedded-hal = { version = "0.2", features = [] }
+shared-bus = { version = "0.2", features = ["cortex-m"] }
+hd44780-driver = { path = "../deps/hd44780-driver"}
+si5351 = { path = "../deps/si5351" }
+
+[profile.dev]
+codegen-units = 1
+incremental = false
+opt-level = 'z'
+
+[profile.release]
+codegen-units = 1
+debug = true
+lto = true
+opt-level = 'z'
diff --git a/sw/eval-clock-cw-tx/Makefile b/sw/eval-clock-cw-tx/Makefile
new file mode 100644
index 0000000..8c5fc79
--- /dev/null
+++ b/sw/eval-clock-cw-tx/Makefile
@@ -0,0 +1,18 @@
+.PHONY: all openocd debug
+
+OPENOCD := openocd
+OPENOCD_OPT := -f interface/stlink-v2.cfg -f target/stm32f1x.cfg
+BIN := target/thumbv7m-none-eabi/debug/picardy
+
+# Build and flash in release mode
+all:
+ cargo build
+ $(OPENOCD) $(OPENOCD_OPT) -c "program $(BIN) reset exit"
+
+# Start a openocd session.
+openocd:
+ $(OPENOCD) $(OPENOCD_OPT)
+
+# Start a gdb session. Works if a valid openocd session is existing.
+debug:
+ arm-none-eabi-gdb $(BIN) -q -x utils/debug.gdb
diff --git a/sw/eval-clock-cw-tx/README.md b/sw/eval-clock-cw-tx/README.md
new file mode 100644
index 0000000..de12a37
--- /dev/null
+++ b/sw/eval-clock-cw-tx/README.md
@@ -0,0 +1,24 @@
+CW TX firmware for eval-clock
+=============================
+
+Mostly the same as ../picardy except where different
+
+pios are different: both Si5351 and display are on same i2c
+
+PB3 is PPTOUTn
+PB15 is CWOUTn
+
+
+Programming
+-----------
+
+Put target in reset
+
+ make openocd
+
+ cargo run
+
+Deassert RESET
+
+ gdb% load
+ gdb% cont
diff --git a/sw/eval-clock-cw-tx/build.rs b/sw/eval-clock-cw-tx/build.rs
new file mode 100644
index 0000000..f2cbda3
--- /dev/null
+++ b/sw/eval-clock-cw-tx/build.rs
@@ -0,0 +1,16 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+ let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+ File::create(out.join("memory.x"))
+ .unwrap()
+ .write_all(include_bytes!("memory.x"))
+ .unwrap();
+
+ println!("cargo:rustc-link-search={}", out.display());
+ println!("cargo:rerun-if-changed=build.rs");
+ println!("cargo:rerun-if-changed=memory.x");
+}
diff --git a/sw/eval-clock-cw-tx/memory.x b/sw/eval-clock-cw-tx/memory.x
new file mode 100644
index 0000000..71f245d
--- /dev/null
+++ b/sw/eval-clock-cw-tx/memory.x
@@ -0,0 +1,6 @@
+/* Linker script for the STM32F103C8T6 */
+MEMORY
+{
+ FLASH : ORIGIN = 0x08000000, LENGTH = 64K
+ RAM : ORIGIN = 0x20000000, LENGTH = 20K
+}
diff --git a/sw/eval-clock-cw-tx/src/cw.rs b/sw/eval-clock-cw-tx/src/cw.rs
new file mode 100644
index 0000000..045ef15
--- /dev/null
+++ b/sw/eval-clock-cw-tx/src/cw.rs
@@ -0,0 +1,200 @@
+//! CW output using PWM on PA8, TIM1 CH1
+
+use stm32f1xx_hal::{
+ prelude::*,
+ timer,
+ pac::TIM1,
+ gpio::gpioa::*,
+ gpio::{Alternate, PushPull},
+ afio::MAPR,
+ pwm,
+};
+
+pub struct CWPWM {
+ channel : pwm::PwmChannel<TIM1, pwm::C1>,
+}
+
+impl CWPWM {
+ pub fn new(pa8: PA8<Alternate<PushPull>>, tim1: timer::Timer<TIM1>, mapr: &mut MAPR) -> Self {
+ let pwm = tim1.pwm(pa8, mapr, 400.hz());
+ let mut channel = pwm.split();
+ channel.enable();
+ channel.set_duty(0);
+ CWPWM { channel }
+ }
+
+ pub fn on(&mut self) {
+ let max = self.channel.get_max_duty();
+ self.channel.set_duty(max / 2);
+ }
+
+ pub fn off(&mut self) {
+ self.channel.set_duty(0);
+ }
+}
+
+#[derive(PartialEq, Eq, Clone, Copy)]
+enum MorseSign {
+ Dot,
+ Dash
+}
+
+impl MorseSign {
+ fn length(&self) -> u32 {
+ match self {
+ Self::Dot => 1,
+ Self::Dash => 3,
+ }
+ }
+
+ fn other(&self) -> Self {
+ match self {
+ Self::Dot => Self::Dash,
+ Self::Dash => Self::Dot,
+ }
+ }
+}
+
+fn other_pressed(sign: MorseSign, dot_pressed: bool, dash_pressed: bool) -> bool {
+ match sign {
+ MorseSign::Dot => dash_pressed,
+ MorseSign::Dash => dot_pressed,
+ }
+}
+
+#[derive(Eq, Clone, Copy)]
+enum KeyerState {
+ Idle,
+ Beep{current: MorseSign, next: Option<MorseSign>},
+ Pause{current: MorseSign, next: Option<MorseSign>},
+ LastPause{next: Option<MorseSign>},
+}
+
+impl PartialEq for KeyerState {
+ fn eq(&self, rhs: &Self) -> bool {
+ match (self, rhs) {
+ (Self::Idle, Self::Idle) => true,
+ (Self::Beep{current : c1, next : _}, Self::Beep{current : c2, next : _}) => c1 == c2,
+ (Self::Pause{current : c1, next : _}, Self::Pause{current : c2, next : _}) => c1 == c2,
+ (Self::LastPause{next : _}, Self::LastPause{next : _}) => true,
+ _ => false,
+ }
+ }
+}
+
+pub struct Keyer {
+ // All durations are in ticks
+ dot_length : u32,
+ state : KeyerState,
+ time_last_state_change : u32,
+}
+
+impl Keyer {
+ pub fn new(wpm : u32, ticks_per_s: u32) -> Keyer {
+ /* PARIS standard: 20 words per minute = dot length of 60 ms, inversely proportional:
+ * 1 wpm = 1200 ms, 2 wpm = 600 ms */
+
+ Keyer{
+ dot_length : 1200 * ticks_per_s / (1000 * wpm),
+ state : KeyerState::Idle,
+ time_last_state_change : 0,
+ }
+ }
+ pub fn set_speed(&mut self, wpm : u32, ticks_per_s: u32) { self.dot_length = 1200 * ticks_per_s / (1000 * wpm) }
+
+ pub fn tick(&mut self, ticks_now: u32, dot_pressed: bool, dash_pressed: bool) -> bool {
+ let mut transmit = false;
+
+ let next_state = match self.state {
+ KeyerState::Idle => {
+ if dot_pressed {
+ transmit = true;
+ KeyerState::Beep{current: MorseSign::Dot, next: None}
+ }
+ else if dash_pressed {
+ transmit = true;
+ KeyerState::Beep{current: MorseSign::Dash, next: None}
+ }
+ else {
+ KeyerState::Idle
+ }
+ },
+ KeyerState::Beep{current, next} => {
+ transmit = true;
+
+ let next = if other_pressed(current, dot_pressed, dash_pressed) {
+ Some(current.other())
+ }
+ else {
+ next
+ };
+
+ if self.time_last_state_change + self.dot_length * current.length() <= ticks_now {
+ KeyerState::Pause{current, next}
+ }
+ else {
+ KeyerState::Beep{current, next}
+ }
+ },
+ KeyerState::Pause{current, next} => {
+ let next = if other_pressed(current, dot_pressed, dash_pressed) {
+ Some(current.other())
+ }
+ else {
+ next
+ };
+
+ if self.time_last_state_change + self.dot_length <= ticks_now {
+ match next {
+ Some(state) => {
+ transmit = true;
+ KeyerState::Beep{current: state, next: None}
+ },
+ None => KeyerState::LastPause{next: None}
+ }
+ }
+ else {
+ KeyerState::Pause{current, next}
+ }
+ },
+ KeyerState::LastPause{next} => {
+ let next = if dot_pressed {
+ Some(MorseSign::Dot)
+ }
+ else if dash_pressed {
+ Some(MorseSign::Dash)
+ }
+ else {
+ next
+ };
+
+ if self.time_last_state_change + self.dot_length <= ticks_now {
+ KeyerState::LastPause{next}
+ }
+ else {
+ match next {
+ Some(MorseSign::Dot) => {
+ transmit = true;
+ KeyerState::Beep{current: MorseSign::Dot, next: None}
+ },
+ Some(MorseSign::Dash) => {
+ transmit = true;
+ KeyerState::Beep{current: MorseSign::Dash, next: None}
+ },
+ None => {
+ KeyerState::Idle
+ },
+ }
+ }
+ },
+ };
+
+ if next_state != self.state {
+ self.time_last_state_change = ticks_now;
+ }
+ self.state = next_state;
+
+ transmit
+ }
+}
+
diff --git a/sw/eval-clock-cw-tx/src/log10f.rs b/sw/eval-clock-cw-tx/src/log10f.rs
new file mode 100644
index 0000000..108dfa8
--- /dev/null
+++ b/sw/eval-clock-cw-tx/src/log10f.rs
@@ -0,0 +1,91 @@
+/* origin: FreeBSD /usr/src/lib/msun/src/e_log10f.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/*
+ * See comments in log10.c.
+ */
+
+use core::f32;
+
+const IVLN10HI: f32 = 4.3432617188e-01; /* 0x3ede6000 */
+const IVLN10LO: f32 = -3.1689971365e-05; /* 0xb804ead9 */
+const LOG10_2HI: f32 = 3.0102920532e-01; /* 0x3e9a2080 */
+const LOG10_2LO: f32 = 7.9034151668e-07; /* 0x355427db */
+/* |(log(1+s)-log(1-s))/s - Lg(s)| < 2**-34.24 (~[-4.95e-11, 4.97e-11]). */
+const LG1: f32 = 0.66666662693; /* 0xaaaaaa.0p-24 */
+const LG2: f32 = 0.40000972152; /* 0xccce13.0p-25 */
+const LG3: f32 = 0.28498786688; /* 0x91e9ee.0p-25 */
+const LG4: f32 = 0.24279078841; /* 0xf89e26.0p-26 */
+
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn log10f(mut x: f32) -> f32 {
+ let x1p25f = f32::from_bits(0x4c000000); // 0x1p25f === 2 ^ 25
+
+ let mut ui: u32 = x.to_bits();
+ let hfsq: f32;
+ let f: f32;
+ let s: f32;
+ let z: f32;
+ let r: f32;
+ let w: f32;
+ let t1: f32;
+ let t2: f32;
+ let dk: f32;
+ let mut hi: f32;
+ let lo: f32;
+ let mut ix: u32;
+ let mut k: i32;
+
+ ix = ui;
+ k = 0;
+ if ix < 0x00800000 || (ix >> 31) > 0 {
+ /* x < 2**-126 */
+ if ix << 1 == 0 {
+ return -1. / (x * x); /* log(+-0)=-inf */
+ }
+ if (ix >> 31) > 0 {
+ return (x - x) / 0.0; /* log(-#) = NaN */
+ }
+ /* subnormal number, scale up x */
+ k -= 25;
+ x *= x1p25f;
+ ui = x.to_bits();
+ ix = ui;
+ } else if ix >= 0x7f800000 {
+ return x;
+ } else if ix == 0x3f800000 {
+ return 0.;
+ }
+
+ /* reduce x into [sqrt(2)/2, sqrt(2)] */
+ ix += 0x3f800000 - 0x3f3504f3;
+ k += (ix >> 23) as i32 - 0x7f;
+ ix = (ix & 0x007fffff) + 0x3f3504f3;
+ ui = ix;
+ x = f32::from_bits(ui);
+
+ f = x - 1.0;
+ s = f / (2.0 + f);
+ z = s * s;
+ w = z * z;
+ t1 = w * (LG2 + w * LG4);
+ t2 = z * (LG1 + w * LG3);
+ r = t2 + t1;
+ hfsq = 0.5 * f * f;
+
+ hi = f - hfsq;
+ ui = hi.to_bits();
+ ui &= 0xfffff000;
+ hi = f32::from_bits(ui);
+ lo = f - hi - hfsq + s * (hfsq + r);
+ dk = k as f32;
+ dk * LOG10_2LO + (lo + hi) * IVLN10LO + lo * IVLN10HI + hi * IVLN10HI + dk * LOG10_2HI
+}
diff --git a/sw/eval-clock-cw-tx/src/main.rs b/sw/eval-clock-cw-tx/src/main.rs
new file mode 100644
index 0000000..4d2dae5
--- /dev/null
+++ b/sw/eval-clock-cw-tx/src/main.rs
@@ -0,0 +1,367 @@
+/*
+ The MIT License (MIT)
+
+ Copyright (c) 2021 Matthias P. Braendli
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in all
+ copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ SOFTWARE.
+*/
+
+#![no_main]
+#![no_std]
+
+use core::mem::MaybeUninit;
+use cortex_m_rt::ExceptionFrame;
+use cortex_m_semihosting::hprintln;
+use panic_semihosting as _;
+
+use stm32f1xx_hal::{
+ prelude::*,
+ pac,
+ pac::interrupt,
+ i2c,
+ gpio,
+ delay::Delay,
+ timer::{CountDownTimer, Timer, Event},
+ qei::QeiOptions,
+};
+
+use embedded_hal::digital::v2::OutputPin;
+use embedded_hal::digital::v2::InputPin;
+use hd44780_driver::{Cursor, CursorBlink, Display, DisplayMode, HD44780};
+
+pub mod ui;
+pub mod cw;
+pub mod state;
+pub mod si_clock;
+pub mod log10f;
+
+use state::*;
+
+const TICKS_PER_SECOND : u32 = 100;
+
+struct SharedWithISR {
+ state : State,
+ last_sequence_state_change : u32,
+ cw_ptt_timestamp : u32,
+ cw_key_n : gpio::gpioa::PA15<gpio::Output<gpio::OpenDrain>>,
+ ui : ui::UI,
+ cw_pwm: cw::CWPWM,
+ cw_keyer: cw::Keyer,
+ cw_paddle_tip: gpio::gpiob::PB8<gpio::Input<gpio::PullUp>>,
+ cw_paddle_ring: gpio::gpiob::PB9<gpio::Input<gpio::PullUp>>,
+ ptt_out_n: gpio::gpiob::PB3<gpio::Output<gpio::PushPull>>,
+ led : gpio::gpiob::PB14<gpio::Output<gpio::PushPull>>,
+}
+
+static mut SHARED: MaybeUninit<SharedWithISR> = MaybeUninit::uninit();
+static mut CLOCK_TIMER: MaybeUninit<CountDownTimer<pac::TIM2>> = MaybeUninit::uninit();
+static mut TICK_COUNTER: MaybeUninit<u32> = MaybeUninit::uninit();
+
+fn ticks_now() -> u32 {
+ cortex_m::interrupt::free(|_cs| unsafe { *TICK_COUNTER.as_ptr() })
+}
+
+fn get_state_copy() -> State {
+ cortex_m::interrupt::free(|_cs| unsafe {
+ (*SHARED.as_ptr()).state.clone()
+ })
+}
+
+#[cortex_m_rt::entry]
+fn main() -> ! {
+ let cp = cortex_m::Peripherals::take().unwrap();
+ let dp = pac::Peripherals::take().unwrap();
+
+ let mut flash = dp.FLASH.constrain();
+ let mut rcc = dp.RCC.constrain();
+ let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
+ let clocks = rcc.cfgr
+ .adcclk(2.mhz())
+ .freeze(&mut flash.acr);
+ let mut delay = Delay::new(cp.SYST, clocks);
+
+ delay.delay_ms(200u16);
+
+ let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
+ let mut gpiob = dp.GPIOB.split(&mut rcc.apb2);
+ let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+
+ // Buttons as analog inputs (multi-level)
+ let pb0 = gpiob.pb0.into_floating_input(&mut gpiob.crl); // BTN1 Button B, has external pullup
+ let pb1 = gpiob.pb1.into_floating_input(&mut gpiob.crl); // BTN0 Button A, has external pullup
+ let pb12 = gpiob.pb12.into_pull_up_input(&mut gpiob.crh); // BTN2 Button C
+ let pb13 = gpiob.pb13.into_pull_up_input(&mut gpiob.crh); // BTN3 Button D
+ let pc15 = gpioc.pc15.into_pull_up_input(&mut gpioc.crh); // Encoder button
+ let ui = ui::UI::new(pb0, pb1, pb12, pb13, pc15);
+
+ let cw_pwm = {
+ let pa8 = gpioa.pa8.into_alternate_push_pull(&mut gpioa.crh); // CW PWM output using TIM1 Ch1
+ let tim1 = Timer::tim1(dp.TIM1, &clocks, &mut rcc.apb2);
+ cw::CWPWM::new(pa8, tim1, &mut afio.mapr)
+ };
+
+ let cw_paddle_tip = gpiob.pb8.into_pull_up_input(&mut gpiob.crh); // CW paddle tip
+ let cw_paddle_ring = gpiob.pb9.into_pull_up_input(&mut gpiob.crh); // CW paddle ring
+
+ // Configure PB14 as output. (LED)
+ let mut led = gpiob.pb14.into_push_pull_output(&mut gpiob.crh);
+ led.set_low().unwrap();
+
+ let (pa15, pb3, _pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4);
+ let cw_key_n = pa15.into_open_drain_output_with_state(&mut gpioa.crh, gpio::State::High);
+ let ptt_out_n = pb3.into_push_pull_output_with_state(&mut gpiob.crl, gpio::State::High);
+
+ let c1 = gpioa.pa6;
+ let c2 = gpioa.pa7;
+ let qei = Timer::tim3(dp.TIM3, &clocks, &mut rcc.apb1)
+ .qei((c1, c2), &mut afio.mapr, QeiOptions::default());
+
+ // Configure I2C1 to be used for Si5351 and display
+ let scl = gpiob.pb6.into_alternate_open_drain(&mut gpiob.crl);
+ let sda = gpiob.pb7.into_alternate_open_drain(&mut gpiob.crl);
+
+ let i2c = i2c::BlockingI2c::i2c1(
+ dp.I2C1,
+ (scl, sda),
+ &mut afio.mapr,
+ i2c::Mode::Standard {
+ frequency: 100_000.hz(),
+ },
+ clocks,
+ &mut rcc.apb1,
+ /* start_timeout_us */ 1000,
+ /* start_retries */ 10,
+ /* addr_timeout_us */ 1000,
+ /* data_timeout_us */ 1000,
+ );
+ let i2c_busmanager = shared_bus::BusManagerSimple::new(i2c);
+
+ const I2C_ADDRESS: u8 = 0b010_0000; // MCP23008, depending on solder bridges
+ let mut lcd = match HD44780::new_i2c_mcp23008(i2c_busmanager.acquire_i2c(), I2C_ADDRESS, &mut delay) {
+ Ok(lcd) => lcd,
+ Err(_) => panic!("HD44780 init fail"),
+ };
+
+ lcd.reset(&mut delay).unwrap();
+ lcd.clear(&mut delay).unwrap();
+ lcd.set_display_mode(
+ DisplayMode {
+ display: Display::On,
+ cursor_visibility: Cursor::Invisible,
+ cursor_blink: CursorBlink::Off,
+ },
+ &mut delay).unwrap();
+ lcd.set_cursor_pos(0, &mut delay).unwrap();
+ lcd.write_str(" HB9EGM ", &mut delay).unwrap();
+ lcd.set_cursor_pos(40, &mut delay).unwrap();
+ lcd.write_str(" 30m CW TX 2021 ", &mut delay).unwrap();
+ delay.delay_ms(1_500u16);
+
+
+ let mut siclock = {
+ let shared = unsafe { &mut *SHARED.as_mut_ptr() };
+ *shared = SharedWithISR {
+ state : State::new(),
+ last_sequence_state_change : 0,
+ cw_ptt_timestamp : 0,
+ cw_key_n,
+ ui,
+ cw_pwm,
+ cw_keyer : cw::Keyer::new(12, TICKS_PER_SECOND),
+ cw_paddle_tip, cw_paddle_ring, ptt_out_n, led
+ };
+
+ si_clock::SiClock::new(i2c_busmanager.acquire_i2c(), 0, shared.state.vfo())
+ };
+
+ ui::update_disp(&mut lcd, &get_state_copy(), &mut delay);
+
+ let mut last_encoder_count = qei.count();
+
+ {
+ let ticks = unsafe { &mut *TICK_COUNTER.as_mut_ptr() };
+ *ticks = 0;
+ }
+
+ {
+ let timer = unsafe { &mut *CLOCK_TIMER.as_mut_ptr() };
+ *timer = Timer::tim2(dp.TIM2, &clocks, &mut rcc.apb1)
+ .start_count_down(TICKS_PER_SECOND.hz());
+ timer.listen(Event::Update);
+ }
+
+ unsafe { pac::NVIC::unmask(pac::Interrupt::TIM2); }
+
+ let mut last_disp_update_counter = 1;
+ let mut previous_vfo = 0;
+
+ loop {
+ let mut update_disp_required = false;
+
+ let state = get_state_copy();
+
+ let encoder_count : u16 = qei.count();
+ if encoder_count != last_encoder_count {
+ let delta = encoder_count.wrapping_sub(last_encoder_count);
+ let delta = if delta > 0x7FFF { delta as i32 - 0x10000 } else { delta as i32 };
+
+ cortex_m::interrupt::free(|_cs| {
+ let shared = unsafe { &mut *SHARED.as_mut_ptr() };
+ shared.ui.update_encoder(&mut shared.state, delta);
+ if let Mode::CW(CWMode::Iambic) = shared.state.mode {
+ shared.cw_keyer.set_speed(shared.state.cw_wpm, TICKS_PER_SECOND)
+ }
+ });
+
+ siclock.set_vfo(state.vfo());
+ update_disp_required = true;
+ }
+
+ let vfo = state.vfo();
+ if previous_vfo != vfo {
+ siclock.set_vfo(vfo);
+ }
+ previous_vfo = vfo;
+
+ if last_disp_update_counter != state.update_disp_counter {
+ update_disp_required = true;
+ last_disp_update_counter = state.update_disp_counter;
+ }
+
+ if update_disp_required {
+ ui::update_disp(&mut lcd, &state, &mut delay);
+ }
+
+ last_encoder_count = encoder_count;
+
+ cortex_m::asm::wfi();
+ }
+}
+
+#[interrupt]
+fn TIM2() {
+ let timer = unsafe { &mut *CLOCK_TIMER.as_mut_ptr() };
+ timer.clear_update_interrupt_flag();
+
+ let ticks = unsafe { &mut *TICK_COUNTER.as_mut_ptr() };
+ *ticks += 1;
+
+ let mut shared = unsafe { &mut *SHARED.as_mut_ptr() };
+ let button_result = shared.ui.handle_buttons(&mut shared.state);
+
+ if button_result.display_update {
+ shared.state.update_disp_counter += 1;
+ }
+
+ let cw_paddle_tip_low = shared.cw_paddle_tip.is_low().unwrap();
+ let cw_paddle_ring_low = shared.cw_paddle_ring.is_low().unwrap();
+
+ let cw_ptt_delay : u32 = TICKS_PER_SECOND * 800 / 1000;
+ let cw_ptt = match shared.state.mode {
+ Mode::CW(_) => {
+ if cw_paddle_tip_low || cw_paddle_ring_low {
+ shared.cw_ptt_timestamp = *ticks;
+ true
+ }
+ else {
+ shared.cw_ptt_timestamp + cw_ptt_delay > *ticks
+ }
+ }
+ };
+
+ let cw_beep = match shared.state.mode {
+ Mode::CW(CWMode::StraightKey) => cw_paddle_tip_low,
+ Mode::CW(CWMode::Iambic) => shared.cw_keyer.tick(*ticks, cw_paddle_tip_low, cw_paddle_ring_low),
+ };
+
+ let next_state = match shared.state.sequence_state {
+ SequenceState::Rx => {
+ shared.ptt_out_n.set_high().unwrap();
+ if cw_ptt {
+ SequenceState::SwitchingCW
+ }
+ else {
+ SequenceState::Rx
+ }
+ },
+ SequenceState::SwitchingCW => {
+ shared.ptt_out_n.set_low().unwrap();
+ if cw_ptt {
+ SequenceState::TxCW
+ }
+ else {
+ SequenceState::Rx
+ }
+ },
+ SequenceState::TxCW => {
+ shared.ptt_out_n.set_low().unwrap();
+ if cw_ptt {
+ SequenceState::TxCW
+ }
+ else {
+ SequenceState::SwitchingCW
+ }
+ },
+ };
+
+ match shared.state.sequence_state {
+ SequenceState::TxCW => {
+ if cw_beep {
+ shared.led.set_low().unwrap();
+ shared.cw_pwm.on();
+ shared.cw_key_n.set_low().unwrap();
+ }
+ else {
+ shared.led.set_high().unwrap();
+ shared.cw_pwm.off();
+ shared.cw_key_n.set_high().unwrap();
+ }
+ },
+ _ => {
+ shared.led.set_high().unwrap();
+ shared.cw_pwm.off();
+ shared.cw_key_n.set_high().unwrap();
+ },
+ }
+
+ const SWITCHING_DELAY : u32 = TICKS_PER_SECOND * 80 / 1000;
+ if shared.state.sequence_state != next_state &&
+ shared.last_sequence_state_change + SWITCHING_DELAY <= *ticks {
+ shared.state.sequence_state = next_state;
+ shared.last_sequence_state_change = *ticks;
+ }
+}
+
+#[cortex_m_rt::exception]
+fn HardFault(ef: &ExceptionFrame) -> ! {
+ let periph = unsafe { cortex_m::Peripherals::steal() };
+ let hfsr = periph.SCB.hfsr.read();
+ let cfsr = periph.SCB.cfsr.read();
+
+ hprintln!("Hardfault {:x} {:x} at {:x}\n", hfsr, cfsr, ef.pc).unwrap();
+ cortex_m::asm::bkpt();
+ loop { }
+}
+
+#[cortex_m_rt::exception]
+fn DefaultHandler(irqn: i16) {
+ hprintln!("Unhandled exception (IRQn = {})", irqn).unwrap();
+ cortex_m::asm::bkpt();
+ loop { }
+}
diff --git a/sw/eval-clock-cw-tx/src/si_clock.rs b/sw/eval-clock-cw-tx/src/si_clock.rs
new file mode 100644
index 0000000..a4b0e7a
--- /dev/null
+++ b/sw/eval-clock-cw-tx/src/si_clock.rs
@@ -0,0 +1,132 @@
+/*
+ The MIT License (MIT)
+
+ Copyright (c) 2020 Matthias P. Braendli
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in all
+ copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ SOFTWARE.
+*/
+use core::convert::TryInto;
+
+use si5351::{Si5351, Si5351Device};
+use embedded_hal::blocking::i2c::{WriteRead, Write};
+
+const REF_CLOCK : u32 = 25_000_000;
+const PLL_A_MULT : u32 = 32;
+
+fn gcd(x: u32, y: u32) -> u32 {
+ let mut x = x;
+ let mut y = y;
+ while y != 0 {
+ let t = y;
+ y = x % y;
+ x = t;
+ }
+ x
+}
+
+fn clock_settings_for_pll(freq: u32, pll: u32) -> (u16, u32, u32) {
+ let a = pll / freq;
+ let b = pll - (a * freq);
+ let gcd = gcd(b, freq);
+
+ let b = b / gcd;
+ let c = freq / gcd;
+ (a.try_into().unwrap(), b, c)
+}
+
+fn clock_settings_with_pll_calculation(freq: u32) -> (u16, u8, u32, u32) {
+ let mut divider : u32 = 900_000_000 / freq; // Calculate the division ratio. 900,000,000 is the maximum internal
+
+ if (divider % 2) == 1 {
+ divider -= 1 // Ensure an even integer division ratio
+ }
+
+ let pll_freq = divider * freq;
+ // mult is an integer that must be in the range 15..90
+ let mult = pll_freq / REF_CLOCK;
+ let l = pll_freq % REF_CLOCK;
+
+ let denom = 1048575;
+ let num = f64::from(l) * f64::from(denom) / f64::from(REF_CLOCK);
+
+ (divider.try_into().unwrap(), mult.try_into().unwrap(), num as u32, denom)
+}
+
+fn set_bfo(siclock: &mut dyn Si5351, freq: u32) -> Result<(), si5351::Error>
+{
+ if freq == 0 {
+ siclock.set_clock_enabled(si5351::ClockOutput::Clk2, false);
+ }
+ else {
+ let (a, b, c) = clock_settings_for_pll(freq, PLL_A_MULT * REF_CLOCK);
+ siclock.setup_multisynth(si5351::Multisynth::MS2, a, b, c, si5351::OutputDivider::Div1)?;
+ siclock.select_clock_pll(si5351::ClockOutput::Clk2, si5351::PLL::A);
+ siclock.set_clock_enabled(si5351::ClockOutput::Clk2, true);
+ }
+ siclock.flush_clock_control(si5351::ClockOutput::Clk2)
+}
+
+fn set_vfo(siclock: &mut dyn Si5351, freq: u32)
+{
+ let (div, mult, num, denom) = clock_settings_with_pll_calculation(freq);
+
+ siclock.setup_pll(si5351::PLL::B, mult, num, denom).unwrap();
+ siclock.setup_multisynth_int(si5351::Multisynth::MS0, div, si5351::OutputDivider::Div1).unwrap();
+ siclock.select_clock_pll(si5351::ClockOutput::Clk0, si5351::PLL::B);
+ siclock.set_clock_enabled(si5351::ClockOutput::Clk0, true);
+ siclock.flush_clock_control(si5351::ClockOutput::Clk0).unwrap();
+}
+
+pub struct SiClock<I2C> {
+ siclock : Si5351Device<I2C>,
+}
+
+impl<I2C, E> SiClock<I2C>
+ where
+ I2C: WriteRead<Error = E> + Write<Error = E>,
+{
+ pub fn new(i2c: I2C, bfo: u32, vfo: u32) -> SiClock<I2C> {
+ let mut siclock = Si5351Device::new(i2c, false, REF_CLOCK);
+ siclock.init(si5351::CrystalLoad::_10).unwrap();
+
+ // See freqplan.py for Si5351 frequency plan
+ // CLK1 unused
+ siclock.setup_pll_int(si5351::PLL::A, 32).unwrap();
+
+ set_bfo(&mut siclock, bfo).unwrap();
+
+ siclock.reset_pll(si5351::PLL::A).unwrap();
+
+ set_vfo(&mut siclock, vfo);
+
+ siclock.reset_pll(si5351::PLL::B).unwrap();
+
+ siclock.flush_output_enabled().unwrap();
+
+ SiClock{siclock}
+ }
+
+ pub fn set_vfo(&mut self, freq: u32) {
+ set_vfo(&mut self.siclock, freq)
+ }
+
+ pub fn set_bfo(&mut self, freq: u32) -> Result<(), si5351::Error> {
+ set_bfo(&mut self.siclock, freq)
+ }
+}
diff --git a/sw/eval-clock-cw-tx/src/state.rs b/sw/eval-clock-cw-tx/src/state.rs
new file mode 100644
index 0000000..b3b0b7b
--- /dev/null
+++ b/sw/eval-clock-cw-tx/src/state.rs
@@ -0,0 +1,83 @@
+const INITIAL_VFO : u32 = 10_100_000;
+
+// Defines which parameter is changed by the encoder
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub enum UISelection {
+ VFO,
+ Mode,
+}
+
+#[derive(Clone, Copy)]
+pub enum VFOSelection {
+ A,
+ B,
+}
+
+#[derive(Clone)]
+pub enum TuneSpeed {
+ Slow,
+ Mid,
+ Fast
+}
+
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum CWMode {
+ StraightKey,
+ Iambic,
+}
+
+#[derive(PartialEq, Eq, Clone, Copy)]
+pub enum Mode {
+ CW(CWMode),
+}
+
+#[derive(Clone, PartialEq, Eq)]
+pub enum SequenceState {
+ Rx,
+ SwitchingCW,
+ TxCW,
+}
+
+#[derive(Clone)]
+pub struct State {
+ pub ui_sel : UISelection,
+ pub vfo_a : u32,
+ pub vfo_b : u32,
+ pub vfo_sel : VFOSelection,
+ pub mode : Mode,
+ pub tune_speed : TuneSpeed,
+ pub sequence_state : SequenceState,
+ pub update_disp_counter : u8,
+ pub cw_wpm : u32,
+}
+
+impl State {
+ pub fn new() -> Self {
+ State {
+ ui_sel : UISelection::VFO,
+ mode : Mode::CW(CWMode::StraightKey),
+ vfo_sel : VFOSelection::A,
+ vfo_a : INITIAL_VFO,
+ vfo_b : INITIAL_VFO,
+ tune_speed : TuneSpeed::Mid,
+ sequence_state : SequenceState::Rx,
+ update_disp_counter : 0,
+ cw_wpm : 12,
+ }
+ }
+
+ pub fn vfo(&self) -> u32 {
+ match self.vfo_sel {
+ VFOSelection::A => self.vfo_a,
+ VFOSelection::B => self.vfo_b,
+ }
+ }
+
+ pub fn vfo_incr(&self) -> i32 {
+ match self.tune_speed {
+ TuneSpeed::Slow => 10,
+ TuneSpeed::Mid => 200,
+ TuneSpeed::Fast => 1000,
+ }
+ }
+}
diff --git a/sw/eval-clock-cw-tx/src/ui.rs b/sw/eval-clock-cw-tx/src/ui.rs
new file mode 100644
index 0000000..564b7d1
--- /dev/null
+++ b/sw/eval-clock-cw-tx/src/ui.rs
@@ -0,0 +1,274 @@
+/*
+ The MIT License (MIT)
+
+ Copyright (c) 2020 Matthias P. Braendli
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in all
+ copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ SOFTWARE.
+*/
+
+use crate::state::*;
+
+use core::fmt;
+use core::fmt::Write;
+
+use stm32f1xx_hal::{
+ delay::Delay,
+ gpio::gpiob::*,
+ gpio::gpioc::*,
+ gpio::{Input, PullUp, Floating},
+};
+
+use embedded_hal::digital::v2::InputPin;
+use hd44780_driver::HD44780;
+
+#[derive(PartialEq, Eq, Clone, Copy)]
+struct ButtonState {
+ pub a : bool,
+ pub b : bool,
+ pub c : bool,
+ pub d : bool,
+ pub e : bool,
+ pub enc : bool,
+}
+
+impl ButtonState {
+ fn edge_detection(&self, old_state : &ButtonState) -> ButtonState {
+ ButtonState {
+ a : !old_state.a && self.a,
+ b : !old_state.b && self.b,
+ c : !old_state.c && self.c,
+ d : !old_state.d && self.d,
+ e : !old_state.e && self.e,
+ enc : !old_state.enc && self.enc,
+ }
+ }
+}
+
+impl Default for ButtonState {
+ fn default() -> Self {
+ ButtonState {
+ a : false,
+ b : false,
+ c : false,
+ d : false,
+ e : false,
+ enc : false,
+ }
+ }
+}
+
+impl fmt::Display for ButtonState {
+ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+ write!(f, "{}{}{}{}{}{}",
+ if self.a { "A" } else { "a" },
+ if self.b { "B" } else { "b" },
+ if self.c { "C" } else { "c" },
+ if self.d { "D" } else { "d" },
+ if self.e { "E" } else { "e" },
+ if self.enc { "X" } else { "x" })
+ }
+}
+
+#[derive(Default)]
+pub struct ButtonResult {
+ pub display_update : bool,
+}
+
+pub struct UI {
+ btn0 : PB1<Input<Floating>>,
+ btn1 : PB0<Input<Floating>>,
+
+ btn2 : PB12<Input<PullUp>>,
+ btn3 : PB13<Input<PullUp>>,
+
+ btn_enc : PC15<Input<PullUp>>,
+
+ previous_button_state : ButtonState,
+}
+
+impl UI {
+ pub fn new(
+ pb0: PB0<Input<Floating>>,
+ pb1: PB1<Input<Floating>>,
+ pb12: PB12<Input<PullUp>>,
+ pb13: PB13<Input<PullUp>>,
+ pc15 : PC15<Input<PullUp>>) -> UI {
+
+ UI {
+ btn0 : pb1,
+ btn1 : pb0,
+ btn2 : pb12,
+ btn3 : pb13,
+ btn_enc : pc15,
+ previous_button_state : ButtonState::default(),
+ }
+ }
+
+ fn read_buttons(&mut self) -> ButtonState {
+ let mut buttons = ButtonState::default();
+
+ let b0_low = self.btn0.is_low().unwrap();
+ let b1_low = self.btn1.is_low().unwrap();
+
+ if b0_low && b1_low {
+ buttons.e = true;
+ }
+ else if b0_low {
+ buttons.a = true;
+ }
+ else if b1_low {
+ buttons.b = true;
+ }
+
+ if self.btn2.is_low().unwrap() {
+ buttons.c = true;
+ }
+
+ if self.btn3.is_low().unwrap() {
+ buttons.d = true;
+ }
+
+ if self.btn_enc.is_low().unwrap() {
+ buttons.enc = true;
+ }
+
+ buttons
+ }
+
+ pub fn handle_buttons(&mut self, state: &mut State) -> ButtonResult {
+ let mut result = ButtonResult::default();
+ let button_state = self.read_buttons();
+ let button_updates = button_state.edge_detection(&self.previous_button_state);
+ self.previous_button_state = button_state;
+
+ if button_updates.a {
+ state.vfo_sel = match (state.ui_sel, state.vfo_sel) {
+ (UISelection::VFO, VFOSelection::A) => VFOSelection::B,
+ (UISelection::VFO, VFOSelection::B) => VFOSelection::A,
+ _ => state.vfo_sel.clone(),
+ };
+ state.ui_sel = UISelection::VFO;
+ result.display_update = true;
+ }
+
+ if button_updates.c {
+ let (new_ui_sel, new_filter_shift) = match (state.ui_sel, state.mode) {
+ (UISelection::Mode, Mode::CW(CWMode::StraightKey)) => (UISelection::Mode, Mode::CW(CWMode::Iambic)),
+ (UISelection::Mode, Mode::CW(CWMode::Iambic)) => (UISelection::Mode, Mode::CW(CWMode::StraightKey)),
+ (_, f) => (UISelection::Mode, f),
+ };
+
+ state.ui_sel = new_ui_sel;
+ state.mode = new_filter_shift;
+
+ result.display_update = true;
+ }
+
+ if button_updates.d {
+ state.tune_speed = match state.tune_speed {
+ TuneSpeed::Slow => TuneSpeed::Mid,
+ TuneSpeed::Mid => TuneSpeed::Fast,
+ TuneSpeed::Fast => TuneSpeed::Slow,
+ };
+ result.display_update = true;
+ }
+
+ if button_updates.enc {
+ match state.ui_sel {
+ UISelection::VFO => {},
+ UISelection::Mode => {
+ state.mode = Mode::CW(CWMode::StraightKey);
+ },
+ }
+
+ result.display_update = true;
+ }
+
+ result
+ }
+
+ // Returns true if bfo must be reprogrammed
+ pub fn update_encoder(&mut self, state: &mut State, delta : i32) {
+ match state.ui_sel {
+ UISelection::VFO => {
+ match state.vfo_sel {
+ VFOSelection::A => {
+ state.vfo_a = (state.vfo_a as i32 + delta * state.vfo_incr()) as u32;
+ },
+ VFOSelection::B => {
+ state.vfo_b = (state.vfo_b as i32 + delta * state.vfo_incr()) as u32;
+ },
+ }
+ },
+ UISelection::Mode => {
+ match state.mode {
+ Mode::CW(CWMode::Iambic) => {
+ let mut new_wpm = state.cw_wpm as i32 + delta / 4;
+ if new_wpm < 1 {
+ new_wpm = 1;
+ }
+
+ let wpm = new_wpm as u32;
+ state.cw_wpm = wpm;
+ state.mode = Mode::CW(CWMode::Iambic);
+ },
+ _ => { },
+ }
+ },
+ }
+ }
+}
+
+pub fn update_disp<T: hd44780_driver::bus::DataBus>(lcd: &mut HD44780<T>, state: &State, delay: &mut Delay)
+{
+ let mut string = arrayvec::ArrayString::<[_; 16]>::new();
+
+ let disp_freq = state.vfo() as i32;
+ write!(string, "{:<05}.{:<03} ", disp_freq / 1000, disp_freq % 1000).unwrap();
+
+ write!(string, " CW{:<02}", state.cw_wpm).unwrap();
+
+ lcd.set_cursor_pos(0, delay).unwrap();
+ lcd.write_str(&string, delay).unwrap();
+
+ string.clear();
+
+ match &state.vfo_sel {
+ VFOSelection::A => write!(string, "VFOa").unwrap(),
+ VFOSelection::B => write!(string, "VFOb").unwrap(),
+ }
+
+ write!(string, " {}", if state.ui_sel == UISelection::Mode { ">" } else { " " }).unwrap();
+
+ let mode = match state.mode {
+ Mode::CW(CWMode::StraightKey) => "CWs",
+ Mode::CW(CWMode::Iambic) => "CWp",
+ };
+
+ let speed = match state.tune_speed {
+ TuneSpeed::Slow => "SLO",
+ TuneSpeed::Mid => "MID",
+ TuneSpeed::Fast => "FST",
+ };
+
+ write!(string, "{} {}", mode, speed).unwrap();
+
+ lcd.set_cursor_pos(40, delay).unwrap();
+ lcd.write_str(&string, delay).unwrap();
+}
diff --git a/sw/eval-clock-cw-tx/utils/STM32H7x3.svd b/sw/eval-clock-cw-tx/utils/STM32H7x3.svd
new file mode 100644
index 0000000..a7ed181
--- /dev/null
+++ b/sw/eval-clock-cw-tx/utils/STM32H7x3.svd
@@ -0,0 +1,101939 @@
+<?xml version="1.0" encoding="utf-8" standalone="no"?>
+<device schemaVersion="1.1"
+xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
+xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+ <name>STM32H7x3</name>
+ <version>1.0</version>
+ <description>STM32H7x3</description>
+ <!--Bus Interface Properties-->
+ <!--Cortex-M3 is byte addressable-->
+ <addressUnitBits>8</addressUnitBits>
+ <!--the maximum data bit width accessible within a single transfer-->
+ <width>32</width>
+ <!--Register Default Properties-->
+ <size>0x20</size>
+ <resetValue>0x0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <peripherals>
+ <peripheral>
+ <name>COMP1</name>
+ <description>COMP1</description>
+ <groupName>COMP1</groupName>
+ <baseAddress>0x58003800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>COMP</name>
+ <description>COMP1 and COMP2</description>
+ <value>137</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>COMP1_SR</name>
+ <displayName>COMP1_SR</displayName>
+ <description>Comparator status register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>C1VAL</name>
+ <description>COMP channel 1 output status
+ bit</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>C2VAL</name>
+ <description>COMP channel 2 output status
+ bit</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>C1IF</name>
+ <description>COMP channel 1 Interrupt
+ Flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>C2IF</name>
+ <description>COMP channel 2 Interrupt
+ Flag</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>COMP1_ICFR</name>
+ <displayName>COMP1_ICFR</displayName>
+ <description>Comparator interrupt clear flag
+ register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CC1IF</name>
+ <description>Clear COMP channel 1 Interrupt
+ Flag</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CC2IF</name>
+ <description>Clear COMP channel 2 Interrupt
+ Flag</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>COMP1_OR</name>
+ <displayName>COMP1_OR</displayName>
+ <description>Comparator option register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>AFOP</name>
+ <description>Selection of source for alternate
+ function of output ports</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>11</bitWidth>
+ </field>
+ <field>
+ <name>OR</name>
+ <description>Option Register</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>21</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>COMP1_CFGR1</name>
+ <displayName>COMP1_CFGR1</displayName>
+ <description>Comparator configuration register
+ 1</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>COMP channel 1 enable bit</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BRGEN</name>
+ <description>Scaler bridge enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCALEN</name>
+ <description>Voltage scaler enable bit</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>POLARITY</name>
+ <description>COMP channel 1 polarity selection
+ bit</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ITEN</name>
+ <description>COMP channel 1 interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HYST</name>
+ <description>COMP channel 1 hysteresis selection
+ bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PWRMODE</name>
+ <description>Power Mode of the COMP channel
+ 1</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>INMSEL</name>
+ <description>COMP channel 1 inverting input selection
+ field</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>INPSEL</name>
+ <description>COMP channel 1 non-inverting input
+ selection bit</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BLANKING</name>
+ <description>COMP channel 1 blanking source selection
+ bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock bit</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>COMP1_CFGR2</name>
+ <displayName>COMP1_CFGR2</displayName>
+ <description>Comparator configuration register
+ 2</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>COMP channel 1 enable bit</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BRGEN</name>
+ <description>Scaler bridge enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SCALEN</name>
+ <description>Voltage scaler enable bit</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>POLARITY</name>
+ <description>COMP channel 1 polarity selection
+ bit</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WINMODE</name>
+ <description>Window comparator mode selection
+ bit</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ITEN</name>
+ <description>COMP channel 1 interrupt
+ enable</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HYST</name>
+ <description>COMP channel 1 hysteresis selection
+ bits</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PWRMODE</name>
+ <description>Power Mode of the COMP channel
+ 1</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>INMSEL</name>
+ <description>COMP channel 1 inverting input selection
+ field</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>INPSEL</name>
+ <description>COMP channel 1 non-inverting input
+ selection bit</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BLANKING</name>
+ <description>COMP channel 1 blanking source selection
+ bits</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock bit</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>CRS</name>
+ <description>CRS</description>
+ <groupName>CRS</groupName>
+ <baseAddress>0x40008400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>CRS</name>
+ <description>Clock Recovery System globa</description>
+ <value>144</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CRS_CR</name>
+ <displayName>CRS_CR</displayName>
+ <description>CRS control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00002000</resetValue>
+ <fields>
+ <field>
+ <name>SYNCOKIE</name>
+ <description>SYNC event OK interrupt
+ enable</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SYNCWARNIE</name>
+ <description>SYNC warning interrupt
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ERRIE</name>
+ <description>Synchronization or trimming error
+ interrupt enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ESYNCIE</name>
+ <description>Expected SYNC interrupt
+ enable</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CEN</name>
+ <description>Frequency error counter enable This bit
+ enables the oscillator clock for the frequency error
+ counter. When this bit is set, the CRS_CFGR register
+ is write-protected and cannot be
+ modified.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>AUTOTRIMEN</name>
+ <description>Automatic trimming enable This bit
+ enables the automatic hardware adjustment of TRIM
+ bits according to the measured frequency error
+ between two SYNC events. If this bit is set, the TRIM
+ bits are read-only. The TRIM value can be adjusted by
+ hardware by one or two steps at a time, depending on
+ the measured frequency error value. Refer to
+ Section7.3.4: Frequency error evaluation and
+ automatic trimming for more details.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>SWSYNC</name>
+ <description>Generate software SYNC event This bit is
+ set by software in order to generate a software SYNC
+ event. It is automatically cleared by
+ hardware.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TRIM</name>
+ <description>HSI48 oscillator smooth trimming These
+ bits provide a user-programmable trimming value to
+ the HSI48 oscillator. They can be programmed to
+ adjust to variations in voltage and temperature that
+ influence the frequency of the HSI48. The default
+ value is 32, which corresponds to the middle of the
+ trimming interval. The trimming step is around 67 kHz
+ between two consecutive TRIM steps. A higher TRIM
+ value corresponds to a higher output frequency. When
+ the AUTOTRIMEN bit is set, this field is controlled
+ by hardware and is read-only.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>6</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CRS_CFGR</name>
+ <displayName>CRS_CFGR</displayName>
+ <description>This register can be written only when the
+ frequency error counter is disabled (CEN bit is cleared
+ in CRS_CR). When the counter is enabled, this register is
+ write-protected.</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x2022BB7F</resetValue>
+ <fields>
+ <field>
+ <name>RELOAD</name>
+ <description>Counter reload value RELOAD is the value
+ to be loaded in the frequency error counter with each
+ SYNC event. Refer to Section7.3.3: Frequency error
+ measurement for more details about counter
+ behavior.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>FELIM</name>
+ <description>Frequency error limit FELIM contains the
+ value to be used to evaluate the captured frequency
+ error value latched in the FECAP[15:0] bits of the
+ CRS_ISR register. Refer to Section7.3.4: Frequency
+ error evaluation and automatic trimming for more
+ details about FECAP evaluation.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SYNCDIV</name>
+ <description>SYNC divider These bits are set and
+ cleared by software to control the division factor of
+ the SYNC signal.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>SYNCSRC</name>
+ <description>SYNC signal source selection These bits
+ are set and cleared by software to select the SYNC
+ signal source. Note: When using USB LPM (Link Power
+ Management) and the device is in Sleep mode, the
+ periodic USB SOF will not be generated by the host.
+ No SYNC signal will therefore be provided to the CRS
+ to calibrate the HSI48 on the run. To guarantee the
+ required clock precision after waking up from Sleep
+ mode, the LSE or reference clock on the GPIOs should
+ be used as SYNC signal.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>SYNCPOL</name>
+ <description>SYNC polarity selection This bit is set
+ and cleared by software to select the input polarity
+ for the SYNC signal source.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CRS_ISR</name>
+ <displayName>CRS_ISR</displayName>
+ <description>CRS interrupt and status
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SYNCOKF</name>
+ <description>SYNC event OK flag This flag is set by
+ hardware when the measured frequency error is smaller
+ than FELIM * 3. This means that either no adjustment
+ of the TRIM value is needed or that an adjustment by
+ one trimming step is enough to compensate the
+ frequency error. An interrupt is generated if the
+ SYNCOKIE bit is set in the CRS_CR register. It is
+ cleared by software by setting the SYNCOKC bit in the
+ CRS_ICR register.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYNCWARNF</name>
+ <description>SYNC warning flag This flag is set by
+ hardware when the measured frequency error is greater
+ than or equal to FELIM * 3, but smaller than FELIM *
+ 128. This means that to compensate the frequency
+ error, the TRIM value must be adjusted by two steps
+ or more. An interrupt is generated if the SYNCWARNIE
+ bit is set in the CRS_CR register. It is cleared by
+ software by setting the SYNCWARNC bit in the CRS_ICR
+ register.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRF</name>
+ <description>Error flag This flag is set by hardware
+ in case of any synchronization or trimming error. It
+ is the logical OR of the TRIMOVF, SYNCMISS and
+ SYNCERR bits. An interrupt is generated if the ERRIE
+ bit is set in the CRS_CR register. It is cleared by
+ software in reaction to setting the ERRC bit in the
+ CRS_ICR register, which clears the TRIMOVF, SYNCMISS
+ and SYNCERR bits.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ESYNCF</name>
+ <description>Expected SYNC flag This flag is set by
+ hardware when the frequency error counter reached a
+ zero value. An interrupt is generated if the ESYNCIE
+ bit is set in the CRS_CR register. It is cleared by
+ software by setting the ESYNCC bit in the CRS_ICR
+ register.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYNCERR</name>
+ <description>SYNC error This flag is set by hardware
+ when the SYNC pulse arrives before the ESYNC event
+ and the measured frequency error is greater than or
+ equal to FELIM * 128. This means that the frequency
+ error is too big (internal frequency too low) to be
+ compensated by adjusting the TRIM value, and that
+ some other action should be taken. An interrupt is
+ generated if the ERRIE bit is set in the CRS_CR
+ register. It is cleared by software by setting the
+ ERRC bit in the CRS_ICR register.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYNCMISS</name>
+ <description>SYNC missed This flag is set by hardware
+ when the frequency error counter reached value FELIM
+ * 128 and no SYNC was detected, meaning either that a
+ SYNC pulse was missed or that the frequency error is
+ too big (internal frequency too high) to be
+ compensated by adjusting the TRIM value, and that
+ some other action should be taken. At this point, the
+ frequency error counter is stopped (waiting for a
+ next SYNC) and an interrupt is generated if the ERRIE
+ bit is set in the CRS_CR register. It is cleared by
+ software by setting the ERRC bit in the CRS_ICR
+ register.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TRIMOVF</name>
+ <description>Trimming overflow or underflow This flag
+ is set by hardware when the automatic trimming tries
+ to over- or under-flow the TRIM value. An interrupt
+ is generated if the ERRIE bit is set in the CRS_CR
+ register. It is cleared by software by setting the
+ ERRC bit in the CRS_ICR register.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FEDIR</name>
+ <description>Frequency error direction FEDIR is the
+ counting direction of the frequency error counter
+ latched in the time of the last SYNC event. It shows
+ whether the actual frequency is below or above the
+ target.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>FECAP</name>
+ <description>Frequency error capture FECAP is the
+ frequency error counter value latched in the time of
+ the last SYNC event. Refer to Section7.3.4: Frequency
+ error evaluation and automatic trimming for more
+ details about FECAP usage.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CRS_ICR</name>
+ <displayName>CRS_ICR</displayName>
+ <description>CRS interrupt flag clear
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SYNCOKC</name>
+ <description>SYNC event OK clear flag Writing 1 to
+ this bit clears the SYNCOKF flag in the CRS_ISR
+ register.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SYNCWARNC</name>
+ <description>SYNC warning clear flag Writing 1 to
+ this bit clears the SYNCWARNF flag in the CRS_ISR
+ register.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRC</name>
+ <description>Error clear flag Writing 1 to this bit
+ clears TRIMOVF, SYNCMISS and SYNCERR bits and
+ consequently also the ERRF flag in the CRS_ISR
+ register.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ESYNCC</name>
+ <description>Expected SYNC clear flag Writing 1 to
+ this bit clears the ESYNCF flag in the CRS_ISR
+ register.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>DAC</name>
+ <description>DAC</description>
+ <groupName>DAC</groupName>
+ <baseAddress>0x40007400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>DAC_CR</name>
+ <displayName>DAC_CR</displayName>
+ <description>DAC control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN1</name>
+ <description>DAC channel1 enable This bit is set and
+ cleared by software to enable/disable DAC
+ channel1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEN1</name>
+ <description>DAC channel1 trigger
+ enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TSEL1</name>
+ <description>DAC channel1 trigger selection These
+ bits select the external event used to trigger DAC
+ channel1. Note: Only used if bit TEN1 = 1 (DAC
+ channel1 trigger enabled).</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>WAVE1</name>
+ <description>DAC channel1 noise/triangle wave
+ generation enable These bits are set and cleared by
+ software. Note: Only used if bit TEN1 = 1 (DAC
+ channel1 trigger enabled).</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MAMP1</name>
+ <description>DAC channel1 mask/amplitude selector
+ These bits are written by software to select mask in
+ wave generation mode or amplitude in triangle
+ generation mode. = 1011: Unmask bits[11:0] of LFSR/
+ triangle amplitude equal to 4095</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN1</name>
+ <description>DAC channel1 DMA enable This bit is set
+ and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAUDRIE1</name>
+ <description>DAC channel1 DMA Underrun Interrupt
+ enable This bit is set and cleared by
+ software.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN1</name>
+ <description>DAC Channel 1 calibration enable This
+ bit is set and cleared by software to enable/disable
+ DAC channel 1 calibration, it can be written only if
+ bit EN1=0 into DAC_CR (the calibration mode can be
+ entered/exit only when the DAC channel is disabled)
+ Otherwise, the write operation is
+ ignored.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EN2</name>
+ <description>DAC channel2 enable This bit is set and
+ cleared by software to enable/disable DAC
+ channel2.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEN2</name>
+ <description>DAC channel2 trigger
+ enable</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TSEL2</name>
+ <description>DAC channel2 trigger selection These
+ bits select the external event used to trigger DAC
+ channel2 Note: Only used if bit TEN2 = 1 (DAC
+ channel2 trigger enabled).</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>WAVE2</name>
+ <description>DAC channel2 noise/triangle wave
+ generation enable These bits are set/reset by
+ software. 1x: Triangle wave generation enabled Note:
+ Only used if bit TEN2 = 1 (DAC channel2 trigger
+ enabled)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MAMP2</name>
+ <description>DAC channel2 mask/amplitude selector
+ These bits are written by software to select mask in
+ wave generation mode or amplitude in triangle
+ generation mode. = 1011: Unmask bits[11:0] of LFSR/
+ triangle amplitude equal to 4095</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DMAEN2</name>
+ <description>DAC channel2 DMA enable This bit is set
+ and cleared by software.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DMAUDRIE2</name>
+ <description>DAC channel2 DMA underrun interrupt
+ enable This bit is set and cleared by
+ software.</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEN2</name>
+ <description>DAC Channel 2 calibration enable This
+ bit is set and cleared by software to enable/disable
+ DAC channel 2 calibration, it can be written only if
+ bit EN2=0 into DAC_CR (the calibration mode can be
+ entered/exit only when the DAC channel is disabled)
+ Otherwise, the write operation is
+ ignored.</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_SWTRGR</name>
+ <displayName>DAC_SWTRGR</displayName>
+ <description>DAC software trigger register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SWTRIG1</name>
+ <description>DAC channel1 software trigger This bit
+ is set by software to trigger the DAC in software
+ trigger mode. Note: This bit is cleared by hardware
+ (one APB1 clock cycle later) once the DAC_DHR1
+ register value has been loaded into the DAC_DOR1
+ register.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SWTRIG2</name>
+ <description>DAC channel2 software trigger This bit
+ is set by software to trigger the DAC in software
+ trigger mode. Note: This bit is cleared by hardware
+ (one APB1 clock cycle later) once the DAC_DHR2
+ register value has been loaded into the DAC_DOR2
+ register.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR12R1</name>
+ <displayName>DAC_DHR12R1</displayName>
+ <description>DAC channel1 12-bit right-aligned data
+ holding register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 12-bit right-aligned data
+ These bits are written by software which specifies
+ 12-bit data for DAC channel1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR12L1</name>
+ <displayName>DAC_DHR12L1</displayName>
+ <description>DAC channel1 12-bit left aligned data
+ holding register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 12-bit left-aligned data
+ These bits are written by software which specifies
+ 12-bit data for DAC channel1.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR8R1</name>
+ <displayName>DAC_DHR8R1</displayName>
+ <description>DAC channel1 8-bit right aligned data
+ holding register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 8-bit right-aligned data
+ These bits are written by software which specifies
+ 8-bit data for DAC channel1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR12R2</name>
+ <displayName>DAC_DHR12R2</displayName>
+ <description>DAC channel2 12-bit right aligned data
+ holding register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 12-bit right-aligned data
+ These bits are written by software which specifies
+ 12-bit data for DAC channel2.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR12L2</name>
+ <displayName>DAC_DHR12L2</displayName>
+ <description>DAC channel2 12-bit left aligned data
+ holding register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 12-bit left-aligned data
+ These bits are written by software which specify
+ 12-bit data for DAC channel2.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR8R2</name>
+ <displayName>DAC_DHR8R2</displayName>
+ <description>DAC channel2 8-bit right-aligned data
+ holding register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 8-bit right-aligned data
+ These bits are written by software which specifies
+ 8-bit data for DAC channel2.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR12RD</name>
+ <displayName>DAC_DHR12RD</displayName>
+ <description>Dual DAC 12-bit right-aligned data holding
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 12-bit right-aligned data
+ These bits are written by software which specifies
+ 12-bit data for DAC channel1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 12-bit right-aligned data
+ These bits are written by software which specifies
+ 12-bit data for DAC channel2.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR12LD</name>
+ <displayName>DAC_DHR12LD</displayName>
+ <description>DUAL DAC 12-bit left aligned data holding
+ register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 12-bit left-aligned data
+ These bits are written by software which specifies
+ 12-bit data for DAC channel1.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 12-bit left-aligned data
+ These bits are written by software which specifies
+ 12-bit data for DAC channel2.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DHR8RD</name>
+ <displayName>DAC_DHR8RD</displayName>
+ <description>DUAL DAC 8-bit right aligned data holding
+ register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DHR</name>
+ <description>DAC channel1 8-bit right-aligned data
+ These bits are written by software which specifies
+ 8-bit data for DAC channel1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>DACC2DHR</name>
+ <description>DAC channel2 8-bit right-aligned data
+ These bits are written by software which specifies
+ 8-bit data for DAC channel2.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DOR1</name>
+ <displayName>DAC_DOR1</displayName>
+ <description>DAC channel1 data output
+ register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC1DOR</name>
+ <description>DAC channel1 data output These bits are
+ read-only, they contain data output for DAC
+ channel1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_DOR2</name>
+ <displayName>DAC_DOR2</displayName>
+ <description>DAC channel2 data output
+ register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DACC2DOR</name>
+ <description>DAC channel2 data output These bits are
+ read-only, they contain data output for DAC
+ channel2.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_SR</name>
+ <displayName>DAC_SR</displayName>
+ <description>DAC status register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAUDR1</name>
+ <description>DAC channel1 DMA underrun flag This bit
+ is set by hardware and cleared by software (by
+ writing it to 1).</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CAL_FLAG1</name>
+ <description>DAC Channel 1 calibration offset status
+ This bit is set and cleared by hardware</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BWST1</name>
+ <description>DAC Channel 1 busy writing sample time
+ flag This bit is systematically set just after Sample
+ &amp; Hold mode enable and is set each time the
+ software writes the register DAC_SHSR1, It is cleared
+ by hardware when the write operation of DAC_SHSR1 is
+ complete. (It takes about 3LSI periods of
+ synchronization).</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DMAUDR2</name>
+ <description>DAC channel2 DMA underrun flag This bit
+ is set by hardware and cleared by software (by
+ writing it to 1).</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CAL_FLAG2</name>
+ <description>DAC Channel 2 calibration offset status
+ This bit is set and cleared by hardware</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BWST2</name>
+ <description>DAC Channel 2 busy writing sample time
+ flag This bit is systematically set just after Sample
+ &amp; Hold mode enable and is set each time the
+ software writes the register DAC_SHSR2, It is cleared
+ by hardware when the write operation of DAC_SHSR2 is
+ complete. (It takes about 3 LSI periods of
+ synchronization).</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_CCR</name>
+ <displayName>DAC_CCR</displayName>
+ <description>DAC calibration control
+ register</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OTRIM1</name>
+ <description>DAC Channel 1 offset trimming
+ value</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OTRIM2</name>
+ <description>DAC Channel 2 offset trimming
+ value</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_MCR</name>
+ <displayName>DAC_MCR</displayName>
+ <description>DAC mode control register</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MODE1</name>
+ <description>DAC Channel 1 mode These bits can be
+ written only when the DAC is disabled and not in the
+ calibration mode (when bit EN1=0 and bit CEN1 =0 in
+ the DAC_CR register). If EN1=1 or CEN1 =1 the write
+ operation is ignored. They can be set and cleared by
+ software to select the DAC Channel 1 mode: DAC
+ Channel 1 in normal Mode DAC Channel 1 in sample
+ &amp;amp; hold mode</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>MODE2</name>
+ <description>DAC Channel 2 mode These bits can be
+ written only when the DAC is disabled and not in the
+ calibration mode (when bit EN2=0 and bit CEN2 =0 in
+ the DAC_CR register). If EN2=1 or CEN2 =1 the write
+ operation is ignored. They can be set and cleared by
+ software to select the DAC Channel 2 mode: DAC
+ Channel 2 in normal Mode DAC Channel 2 in sample
+ &amp;amp; hold mode</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_SHSR1</name>
+ <displayName>DAC_SHSR1</displayName>
+ <description>DAC Sample and Hold sample time register
+ 1</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TSAMPLE1</name>
+ <description>DAC Channel 1 sample Time (only valid in
+ sample &amp;amp; hold mode) These bits can be written
+ when the DAC channel1 is disabled or also during
+ normal operation. in the latter case, the write can
+ be done only when BWSTx of DAC_SR register is low, If
+ BWSTx=1, the write operation is
+ ignored.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_SHSR2</name>
+ <displayName>DAC_SHSR2</displayName>
+ <description>DAC Sample and Hold sample time register
+ 2</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TSAMPLE2</name>
+ <description>DAC Channel 2 sample Time (only valid in
+ sample &amp;amp; hold mode) These bits can be written
+ when the DAC channel2 is disabled or also during
+ normal operation. in the latter case, the write can
+ be done only when BWSTx of DAC_SR register is low, if
+ BWSTx=1, the write operation is
+ ignored.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_SHHR</name>
+ <displayName>DAC_SHHR</displayName>
+ <description>DAC Sample and Hold hold time
+ register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00010001</resetValue>
+ <fields>
+ <field>
+ <name>THOLD1</name>
+ <description>DAC Channel 1 hold Time (only valid in
+ sample &amp;amp; hold mode) Hold time= (THOLD[9:0]) x
+ T LSI</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>THOLD2</name>
+ <description>DAC Channel 2 hold time (only valid in
+ sample &amp;amp; hold mode). Hold time= (THOLD[9:0])
+ x T LSI</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAC_SHRR</name>
+ <displayName>DAC_SHRR</displayName>
+ <description>DAC Sample and Hold refresh time
+ register</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00010001</resetValue>
+ <fields>
+ <field>
+ <name>TREFRESH1</name>
+ <description>DAC Channel 1 refresh Time (only valid
+ in sample &amp;amp; hold mode) Refresh time=
+ (TREFRESH[7:0]) x T LSI</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>TREFRESH2</name>
+ <description>DAC Channel 2 refresh Time (only valid
+ in sample &amp;amp; hold mode) Refresh time=
+ (TREFRESH[7:0]) x T LSI</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>BDMA</name>
+ <description>BDMA</description>
+ <groupName>BDMA</groupName>
+ <baseAddress>0x58025400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>BDMA_CH1</name>
+ <description>BDMA channel 1 interrupt</description>
+ <value>129</value>
+ </interrupt>
+ <interrupt>
+ <name>BDMA_CH2</name>
+ <description>BDMA channel 2 interrupt</description>
+ <value>130</value>
+ </interrupt>
+ <interrupt>
+ <name>BDMA_CH3</name>
+ <description>BDMA channel 3 interrupt</description>
+ <value>131</value>
+ </interrupt>
+ <interrupt>
+ <name>BDMA_CH4</name>
+ <description>BDMA channel 4 interrupt</description>
+ <value>132</value>
+ </interrupt>
+ <interrupt>
+ <name>BDMA_CH5</name>
+ <description>BDMA channel 5 interrupt</description>
+ <value>133</value>
+ </interrupt>
+ <interrupt>
+ <name>BDMA_CH6</name>
+ <description>BDMA channel 6 interrupt</description>
+ <value>134</value>
+ </interrupt>
+ <interrupt>
+ <name>BDMA_CH7</name>
+ <description>BDMA channel 7 interrupt</description>
+ <value>135</value>
+ </interrupt>
+ <interrupt>
+ <name>BDMA_CH8</name>
+ <description>BDMA channel 8 interrupt</description>
+ <value>136</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>BDMA_ISR</name>
+ <displayName>BDMA_ISR</displayName>
+ <description>DMA interrupt status register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>GIF1</name>
+ <description>Channel x global interrupt flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF1</name>
+ <description>Channel x transfer complete flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF1</name>
+ <description>Channel x half transfer flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF1</name>
+ <description>Channel x transfer error flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GIF2</name>
+ <description>Channel x global interrupt flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF2</name>
+ <description>Channel x transfer complete flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF2</name>
+ <description>Channel x half transfer flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF2</name>
+ <description>Channel x transfer error flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GIF3</name>
+ <description>Channel x global interrupt flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF3</name>
+ <description>Channel x transfer complete flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF3</name>
+ <description>Channel x half transfer flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF3</name>
+ <description>Channel x transfer error flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GIF4</name>
+ <description>Channel x global interrupt flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF4</name>
+ <description>Channel x transfer complete flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF4</name>
+ <description>Channel x half transfer flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF4</name>
+ <description>Channel x transfer error flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GIF5</name>
+ <description>Channel x global interrupt flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF5</name>
+ <description>Channel x transfer complete flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF5</name>
+ <description>Channel x half transfer flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF5</name>
+ <description>Channel x transfer error flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GIF6</name>
+ <description>Channel x global interrupt flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF6</name>
+ <description>Channel x transfer complete flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF6</name>
+ <description>Channel x half transfer flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF6</name>
+ <description>Channel x transfer error flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GIF7</name>
+ <description>Channel x global interrupt flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF7</name>
+ <description>Channel x transfer complete flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF7</name>
+ <description>Channel x half transfer flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF7</name>
+ <description>Channel x transfer error flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GIF8</name>
+ <description>Channel x global interrupt flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF8</name>
+ <description>Channel x transfer complete flag (x =
+ 1..8) This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIF8</name>
+ <description>Channel x half transfer flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIF8</name>
+ <description>Channel x transfer error flag (x = 1..8)
+ This bit is set by hardware. It is cleared by
+ software writing 1 to the corresponding bit in the
+ DMA_IFCR register.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_IFCR</name>
+ <displayName>BDMA_IFCR</displayName>
+ <description>DMA interrupt flag clear
+ register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CGIF1</name>
+ <description>Channel x global interrupt clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF1</name>
+ <description>Channel x transfer complete clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF1</name>
+ <description>Channel x half transfer clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF1</name>
+ <description>Channel x transfer error clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CGIF2</name>
+ <description>Channel x global interrupt clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF2</name>
+ <description>Channel x transfer complete clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF2</name>
+ <description>Channel x half transfer clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF2</name>
+ <description>Channel x transfer error clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CGIF3</name>
+ <description>Channel x global interrupt clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF3</name>
+ <description>Channel x transfer complete clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF3</name>
+ <description>Channel x half transfer clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF3</name>
+ <description>Channel x transfer error clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CGIF4</name>
+ <description>Channel x global interrupt clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF4</name>
+ <description>Channel x transfer complete clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF4</name>
+ <description>Channel x half transfer clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF4</name>
+ <description>Channel x transfer error clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CGIF5</name>
+ <description>Channel x global interrupt clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF5</name>
+ <description>Channel x transfer complete clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF5</name>
+ <description>Channel x half transfer clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF5</name>
+ <description>Channel x transfer error clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CGIF6</name>
+ <description>Channel x global interrupt clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF6</name>
+ <description>Channel x transfer complete clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF6</name>
+ <description>Channel x half transfer clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF6</name>
+ <description>Channel x transfer error clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CGIF7</name>
+ <description>Channel x global interrupt clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF7</name>
+ <description>Channel x transfer complete clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF7</name>
+ <description>Channel x half transfer clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF7</name>
+ <description>Channel x transfer error clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CGIF8</name>
+ <description>Channel x global interrupt clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF8</name>
+ <description>Channel x transfer complete clear This
+ bit is set and cleared by software.</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CHTIF8</name>
+ <description>Channel x half transfer clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTEIF8</name>
+ <description>Channel x transfer error clear This bit
+ is set and cleared by software.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CCR1</name>
+ <displayName>BDMA_CCR1</displayName>
+ <description>DMA channel x configuration
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Channel enable This bit is set and
+ cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction This bit is set
+ and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode This bit is
+ set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral size These bits are set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory size These bits are set and
+ cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Channel priority level These bits are
+ set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MEM2MEM</name>
+ <description>Memory to memory mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CNDTR1</name>
+ <displayName>BDMA_CNDTR1</displayName>
+ <description>DMA channel x number of data
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data to transfer Number of
+ data to be transferred (0 up to 65535). This register
+ can only be written when the channel is disabled.
+ Once the channel is enabled, this register is
+ read-only, indicating the remaining bytes to be
+ transmitted. This register decrements after each DMA
+ transfer. Once the transfer is completed, this
+ register can either stay at zero or be reloaded
+ automatically by the value previously programmed if
+ the channel is configured in auto-reload mode. If
+ this register is zero, no transaction can be served
+ whether the channel is enabled or not.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CPAR1</name>
+ <displayName>BDMA_CPAR1</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address Base address of the
+ peripheral data register from/to which the data will
+ be read/written. When PSIZE is 01 (16-bit), the PA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When PSIZE is 10 (32-bit), PA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CMAR1</name>
+ <displayName>BDMA_CMAR1</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Base address of the
+ memory area from/to which the data will be
+ read/written. When MSIZE is 01 (16-bit), the MA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When MSIZE is 10 (32-bit), MA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CCR2</name>
+ <displayName>BDMA_CCR2</displayName>
+ <description>DMA channel x configuration
+ register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Channel enable This bit is set and
+ cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction This bit is set
+ and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode This bit is
+ set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral size These bits are set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory size These bits are set and
+ cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Channel priority level These bits are
+ set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MEM2MEM</name>
+ <description>Memory to memory mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CNDTR2</name>
+ <displayName>BDMA_CNDTR2</displayName>
+ <description>DMA channel x number of data
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data to transfer Number of
+ data to be transferred (0 up to 65535). This register
+ can only be written when the channel is disabled.
+ Once the channel is enabled, this register is
+ read-only, indicating the remaining bytes to be
+ transmitted. This register decrements after each DMA
+ transfer. Once the transfer is completed, this
+ register can either stay at zero or be reloaded
+ automatically by the value previously programmed if
+ the channel is configured in auto-reload mode. If
+ this register is zero, no transaction can be served
+ whether the channel is enabled or not.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CPAR2</name>
+ <displayName>BDMA_CPAR2</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address Base address of the
+ peripheral data register from/to which the data will
+ be read/written. When PSIZE is 01 (16-bit), the PA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When PSIZE is 10 (32-bit), PA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CMAR2</name>
+ <displayName>BDMA_CMAR2</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Base address of the
+ memory area from/to which the data will be
+ read/written. When MSIZE is 01 (16-bit), the MA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When MSIZE is 10 (32-bit), MA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CCR3</name>
+ <displayName>BDMA_CCR3</displayName>
+ <description>DMA channel x configuration
+ register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Channel enable This bit is set and
+ cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction This bit is set
+ and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode This bit is
+ set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral size These bits are set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory size These bits are set and
+ cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Channel priority level These bits are
+ set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MEM2MEM</name>
+ <description>Memory to memory mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CNDTR3</name>
+ <displayName>BDMA_CNDTR3</displayName>
+ <description>DMA channel x number of data
+ register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data to transfer Number of
+ data to be transferred (0 up to 65535). This register
+ can only be written when the channel is disabled.
+ Once the channel is enabled, this register is
+ read-only, indicating the remaining bytes to be
+ transmitted. This register decrements after each DMA
+ transfer. Once the transfer is completed, this
+ register can either stay at zero or be reloaded
+ automatically by the value previously programmed if
+ the channel is configured in auto-reload mode. If
+ this register is zero, no transaction can be served
+ whether the channel is enabled or not.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CPAR3</name>
+ <displayName>BDMA_CPAR3</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address Base address of the
+ peripheral data register from/to which the data will
+ be read/written. When PSIZE is 01 (16-bit), the PA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When PSIZE is 10 (32-bit), PA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CMAR3</name>
+ <displayName>BDMA_CMAR3</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Base address of the
+ memory area from/to which the data will be
+ read/written. When MSIZE is 01 (16-bit), the MA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When MSIZE is 10 (32-bit), MA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CCR4</name>
+ <displayName>BDMA_CCR4</displayName>
+ <description>DMA channel x configuration
+ register</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Channel enable This bit is set and
+ cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction This bit is set
+ and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode This bit is
+ set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral size These bits are set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory size These bits are set and
+ cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Channel priority level These bits are
+ set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MEM2MEM</name>
+ <description>Memory to memory mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CNDTR4</name>
+ <displayName>BDMA_CNDTR4</displayName>
+ <description>DMA channel x number of data
+ register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data to transfer Number of
+ data to be transferred (0 up to 65535). This register
+ can only be written when the channel is disabled.
+ Once the channel is enabled, this register is
+ read-only, indicating the remaining bytes to be
+ transmitted. This register decrements after each DMA
+ transfer. Once the transfer is completed, this
+ register can either stay at zero or be reloaded
+ automatically by the value previously programmed if
+ the channel is configured in auto-reload mode. If
+ this register is zero, no transaction can be served
+ whether the channel is enabled or not.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CPAR4</name>
+ <displayName>BDMA_CPAR4</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address Base address of the
+ peripheral data register from/to which the data will
+ be read/written. When PSIZE is 01 (16-bit), the PA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When PSIZE is 10 (32-bit), PA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CMAR4</name>
+ <displayName>BDMA_CMAR4</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Base address of the
+ memory area from/to which the data will be
+ read/written. When MSIZE is 01 (16-bit), the MA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When MSIZE is 10 (32-bit), MA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CCR5</name>
+ <displayName>BDMA_CCR5</displayName>
+ <description>DMA channel x configuration
+ register</description>
+ <addressOffset>0x58</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Channel enable This bit is set and
+ cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction This bit is set
+ and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode This bit is
+ set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral size These bits are set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory size These bits are set and
+ cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Channel priority level These bits are
+ set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MEM2MEM</name>
+ <description>Memory to memory mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CNDTR5</name>
+ <displayName>BDMA_CNDTR5</displayName>
+ <description>DMA channel x number of data
+ register</description>
+ <addressOffset>0x5C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data to transfer Number of
+ data to be transferred (0 up to 65535). This register
+ can only be written when the channel is disabled.
+ Once the channel is enabled, this register is
+ read-only, indicating the remaining bytes to be
+ transmitted. This register decrements after each DMA
+ transfer. Once the transfer is completed, this
+ register can either stay at zero or be reloaded
+ automatically by the value previously programmed if
+ the channel is configured in auto-reload mode. If
+ this register is zero, no transaction can be served
+ whether the channel is enabled or not.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CPAR5</name>
+ <displayName>BDMA_CPAR5</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x60</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address Base address of the
+ peripheral data register from/to which the data will
+ be read/written. When PSIZE is 01 (16-bit), the PA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When PSIZE is 10 (32-bit), PA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CMAR5</name>
+ <displayName>BDMA_CMAR5</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x64</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Base address of the
+ memory area from/to which the data will be
+ read/written. When MSIZE is 01 (16-bit), the MA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When MSIZE is 10 (32-bit), MA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CCR6</name>
+ <displayName>BDMA_CCR6</displayName>
+ <description>DMA channel x configuration
+ register</description>
+ <addressOffset>0x6C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Channel enable This bit is set and
+ cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction This bit is set
+ and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode This bit is
+ set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral size These bits are set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory size These bits are set and
+ cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Channel priority level These bits are
+ set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MEM2MEM</name>
+ <description>Memory to memory mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CNDTR6</name>
+ <displayName>BDMA_CNDTR6</displayName>
+ <description>DMA channel x number of data
+ register</description>
+ <addressOffset>0x70</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data to transfer Number of
+ data to be transferred (0 up to 65535). This register
+ can only be written when the channel is disabled.
+ Once the channel is enabled, this register is
+ read-only, indicating the remaining bytes to be
+ transmitted. This register decrements after each DMA
+ transfer. Once the transfer is completed, this
+ register can either stay at zero or be reloaded
+ automatically by the value previously programmed if
+ the channel is configured in auto-reload mode. If
+ this register is zero, no transaction can be served
+ whether the channel is enabled or not.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CPAR6</name>
+ <displayName>BDMA_CPAR6</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x74</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address Base address of the
+ peripheral data register from/to which the data will
+ be read/written. When PSIZE is 01 (16-bit), the PA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When PSIZE is 10 (32-bit), PA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CMAR6</name>
+ <displayName>BDMA_CMAR6</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x78</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Base address of the
+ memory area from/to which the data will be
+ read/written. When MSIZE is 01 (16-bit), the MA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When MSIZE is 10 (32-bit), MA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CCR7</name>
+ <displayName>BDMA_CCR7</displayName>
+ <description>DMA channel x configuration
+ register</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Channel enable This bit is set and
+ cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction This bit is set
+ and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode This bit is
+ set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral size These bits are set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory size These bits are set and
+ cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Channel priority level These bits are
+ set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MEM2MEM</name>
+ <description>Memory to memory mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CNDTR7</name>
+ <displayName>BDMA_CNDTR7</displayName>
+ <description>DMA channel x number of data
+ register</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data to transfer Number of
+ data to be transferred (0 up to 65535). This register
+ can only be written when the channel is disabled.
+ Once the channel is enabled, this register is
+ read-only, indicating the remaining bytes to be
+ transmitted. This register decrements after each DMA
+ transfer. Once the transfer is completed, this
+ register can either stay at zero or be reloaded
+ automatically by the value previously programmed if
+ the channel is configured in auto-reload mode. If
+ this register is zero, no transaction can be served
+ whether the channel is enabled or not.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CPAR7</name>
+ <displayName>BDMA_CPAR7</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x88</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address Base address of the
+ peripheral data register from/to which the data will
+ be read/written. When PSIZE is 01 (16-bit), the PA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When PSIZE is 10 (32-bit), PA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CMAR7</name>
+ <displayName>BDMA_CMAR7</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x8C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Base address of the
+ memory area from/to which the data will be
+ read/written. When MSIZE is 01 (16-bit), the MA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When MSIZE is 10 (32-bit), MA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CCR8</name>
+ <displayName>BDMA_CCR8</displayName>
+ <description>DMA channel x configuration
+ register</description>
+ <addressOffset>0x94</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Channel enable This bit is set and
+ cleared by software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HTIE</name>
+ <description>Half transfer interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Data transfer direction This bit is set
+ and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CIRC</name>
+ <description>Circular mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PINC</name>
+ <description>Peripheral increment mode This bit is
+ set and cleared by software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MINC</name>
+ <description>Memory increment mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PSIZE</name>
+ <description>Peripheral size These bits are set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MSIZE</name>
+ <description>Memory size These bits are set and
+ cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Channel priority level These bits are
+ set and cleared by software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MEM2MEM</name>
+ <description>Memory to memory mode This bit is set
+ and cleared by software.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CNDTR8</name>
+ <displayName>BDMA_CNDTR8</displayName>
+ <description>DMA channel x number of data
+ register</description>
+ <addressOffset>0x98</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NDT</name>
+ <description>Number of data to transfer Number of
+ data to be transferred (0 up to 65535). This register
+ can only be written when the channel is disabled.
+ Once the channel is enabled, this register is
+ read-only, indicating the remaining bytes to be
+ transmitted. This register decrements after each DMA
+ transfer. Once the transfer is completed, this
+ register can either stay at zero or be reloaded
+ automatically by the value previously programmed if
+ the channel is configured in auto-reload mode. If
+ this register is zero, no transaction can be served
+ whether the channel is enabled or not.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CPAR8</name>
+ <displayName>BDMA_CPAR8</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0x9C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PA</name>
+ <description>Peripheral address Base address of the
+ peripheral data register from/to which the data will
+ be read/written. When PSIZE is 01 (16-bit), the PA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When PSIZE is 10 (32-bit), PA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BDMA_CMAR8</name>
+ <displayName>BDMA_CMAR8</displayName>
+ <description>This register must not be written when the
+ channel is enabled.</description>
+ <addressOffset>0xA0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Base address of the
+ memory area from/to which the data will be
+ read/written. When MSIZE is 01 (16-bit), the MA[0]
+ bit is ignored. Access is automatically aligned to a
+ half-word address. When MSIZE is 10 (32-bit), MA[1:0]
+ are ignored. Access is automatically aligned to a
+ word address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>DMA2D</name>
+ <description>DMA2D</description>
+ <groupName>DMA2D</groupName>
+ <baseAddress>0x52001000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>DMA2D</name>
+ <description>DMA2D global interrupt</description>
+ <value>90</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>DMA2D_CR</name>
+ <displayName>DMA2D_CR</displayName>
+ <description>DMA2D control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>START</name>
+ <description>Start This bit can be used to launch the
+ DMA2D according to the parameters loaded in the
+ various configuration registers</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SUSP</name>
+ <description>Suspend This bit can be used to suspend
+ the current transfer. This bit is set and reset by
+ software. It is automatically reset by hardware when
+ the START bit is reset.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ABORT</name>
+ <description>Abort This bit can be used to abort the
+ current transfer. This bit is set by software and is
+ automatically reset by hardware when the START bit is
+ reset.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TEIE</name>
+ <description>Transfer error interrupt enable This bit
+ is set and cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer complete interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TWIE</name>
+ <description>Transfer watermark interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAEIE</name>
+ <description>CLUT access error interrupt enable This
+ bit is set and cleared by software.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIE</name>
+ <description>CLUT transfer complete interrupt enable
+ This bit is set and cleared by
+ software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEIE</name>
+ <description>Configuration Error Interrupt Enable
+ This bit is set and cleared by
+ software.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MODE</name>
+ <description>DMA2D mode This bit is set and cleared
+ by software. It cannot be modified while a transfer
+ is ongoing.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_ISR</name>
+ <displayName>DMA2D_ISR</displayName>
+ <description>DMA2D Interrupt Status
+ Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TEIF</name>
+ <description>Transfer error interrupt flag This bit
+ is set when an error occurs during a DMA transfer
+ (data transfer or automatic CLUT
+ loading).</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIF</name>
+ <description>Transfer complete interrupt flag This
+ bit is set when a DMA2D transfer operation is
+ complete (data transfer only).</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TWIF</name>
+ <description>Transfer watermark interrupt flag This
+ bit is set when the last pixel of the watermarked
+ line has been transferred.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAEIF</name>
+ <description>CLUT access error interrupt flag This
+ bit is set when the CPU accesses the CLUT while the
+ CLUT is being automatically copied from a system
+ memory to the internal DMA2D.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF</name>
+ <description>CLUT transfer complete interrupt flag
+ This bit is set when the CLUT copy from a system
+ memory area to the internal DMA2D memory is
+ complete.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CEIF</name>
+ <description>Configuration error interrupt flag This
+ bit is set when the START bit of DMA2D_CR,
+ DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong
+ configuration has been programmed.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_IFCR</name>
+ <displayName>DMA2D_IFCR</displayName>
+ <description>DMA2D interrupt flag clear
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CTEIF</name>
+ <description>Clear Transfer error interrupt flag
+ Programming this bit to 1 clears the TEIF flag in the
+ DMA2D_ISR register</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTCIF</name>
+ <description>Clear transfer complete interrupt flag
+ Programming this bit to 1 clears the TCIF flag in the
+ DMA2D_ISR register</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTWIF</name>
+ <description>Clear transfer watermark interrupt flag
+ Programming this bit to 1 clears the TWIF flag in the
+ DMA2D_ISR register</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAECIF</name>
+ <description>Clear CLUT access error interrupt flag
+ Programming this bit to 1 clears the CAEIF flag in
+ the DMA2D_ISR register</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCTCIF</name>
+ <description>Clear CLUT transfer complete interrupt
+ flag Programming this bit to 1 clears the CTCIF flag
+ in the DMA2D_ISR register</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCEIF</name>
+ <description>Clear configuration error interrupt flag
+ Programming this bit to 1 clears the CEIF flag in the
+ DMA2D_ISR register</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_FGMAR</name>
+ <displayName>DMA2D_FGMAR</displayName>
+ <description>DMA2D foreground memory address
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Address of the data used
+ for the foreground image. This register can only be
+ written when data transfers are disabled. Once the
+ data transfer has started, this register is
+ read-only. The address alignment must match the image
+ format selected e.g. a 32-bit per pixel format must
+ be 32-bit aligned, a 16-bit per pixel format must be
+ 16-bit aligned and a 4-bit per pixel format must be
+ 8-bit aligned.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_FGOR</name>
+ <displayName>DMA2D_FGOR</displayName>
+ <description>DMA2D foreground offset
+ register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LO</name>
+ <description>Line offset Line offset used for the
+ foreground expressed in pixel. This value is used to
+ generate the address. It is added at the end of each
+ line to determine the starting address of the next
+ line. These bits can only be written when data
+ transfers are disabled. Once a data transfer has
+ started, they become read-only. If the image format
+ is 4-bit per pixel, the line offset must be
+ even.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>14</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_BGMAR</name>
+ <displayName>DMA2D_BGMAR</displayName>
+ <description>DMA2D background memory address
+ register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Address of the data used
+ for the background image. This register can only be
+ written when data transfers are disabled. Once a data
+ transfer has started, this register is read-only. The
+ address alignment must match the image format
+ selected e.g. a 32-bit per pixel format must be
+ 32-bit aligned, a 16-bit per pixel format must be
+ 16-bit aligned and a 4-bit per pixel format must be
+ 8-bit aligned.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_BGOR</name>
+ <displayName>DMA2D_BGOR</displayName>
+ <description>DMA2D background offset
+ register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LO</name>
+ <description>Line offset Line offset used for the
+ background image (expressed in pixel). This value is
+ used for the address generation. It is added at the
+ end of each line to determine the starting address of
+ the next line. These bits can only be written when
+ data transfers are disabled. Once data transfer has
+ started, they become read-only. If the image format
+ is 4-bit per pixel, the line offset must be
+ even.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>14</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_FGPFCCR</name>
+ <displayName>DMA2D_FGPFCCR</displayName>
+ <description>DMA2D foreground PFC control
+ register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CM</name>
+ <description>Color mode These bits defines the color
+ format of the foreground image. They can only be
+ written when data transfers are disabled. Once the
+ transfer has started, they are read-only. others:
+ meaningless</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CCM</name>
+ <description>CLUT color mode This bit defines the
+ color format of the CLUT. It can only be written when
+ the transfer is disabled. Once the CLUT transfer has
+ started, this bit is read-only.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>START</name>
+ <description>Start This bit can be set to start the
+ automatic loading of the CLUT. It is automatically
+ reset: ** at the end of the transfer ** when the
+ transfer is aborted by the user application by
+ setting the ABORT bit in DMA2D_CR ** when a transfer
+ error occurs ** when the transfer has not started due
+ to a configuration error or another transfer
+ operation already ongoing (data transfer or automatic
+ background CLUT transfer).</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CS</name>
+ <description>CLUT size These bits define the size of
+ the CLUT used for the foreground image. Once the CLUT
+ transfer has started, this field is read-only. The
+ number of CLUT entries is equal to CS[7:0] +
+ 1.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>AM</name>
+ <description>Alpha mode These bits select the alpha
+ channel value to be used for the foreground image.
+ They can only be written data the transfer are
+ disabled. Once the transfer has started, they become
+ read-only. other configurations are
+ meaningless</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>CSS</name>
+ <description>Chroma Sub-Sampling These bits define
+ the chroma sub-sampling mode for YCbCr color mode.
+ Once the transfer has started, these bits are
+ read-only. others: meaningless</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AI</name>
+ <description>Alpha Inverted This bit inverts the
+ alpha value. Once the transfer has started, this bit
+ is read-only.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RBS</name>
+ <description>Red Blue Swap This bit allows to swap
+ the R &amp;amp; B to support BGR or ABGR color
+ formats. Once the transfer has started, this bit is
+ read-only.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALPHA</name>
+ <description>Alpha value These bits define a fixed
+ alpha channel value which can replace the original
+ alpha value or be multiplied by the original alpha
+ value according to the alpha mode selected through
+ the AM[1:0] bits. These bits can only be written when
+ data transfers are disabled. Once a transfer has
+ started, they become read-only.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_FGCOLR</name>
+ <displayName>DMA2D_FGCOLR</displayName>
+ <description>DMA2D foreground color
+ register</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BLUE</name>
+ <description>Blue Value These bits defines the blue
+ value for the A4 or A8 mode of the foreground image.
+ They can only be written when data transfers are
+ disabled. Once the transfer has started, They are
+ read-only.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>GREEN</name>
+ <description>Green Value These bits defines the green
+ value for the A4 or A8 mode of the foreground image.
+ They can only be written when data transfers are
+ disabled. Once the transfer has started, They are
+ read-only.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RED</name>
+ <description>Red Value These bits defines the red
+ value for the A4 or A8 mode of the foreground image.
+ They can only be written when data transfers are
+ disabled. Once the transfer has started, they are
+ read-only.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_BGPFCCR</name>
+ <displayName>DMA2D_BGPFCCR</displayName>
+ <description>DMA2D background PFC control
+ register</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CM</name>
+ <description>Color mode These bits define the color
+ format of the foreground image. These bits can only
+ be written when data transfers are disabled. Once the
+ transfer has started, they are read-only. others:
+ meaningless</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CCM</name>
+ <description>CLUT Color mode These bits define the
+ color format of the CLUT. This register can only be
+ written when the transfer is disabled. Once the CLUT
+ transfer has started, this bit is
+ read-only.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>START</name>
+ <description>Start This bit is set to start the
+ automatic loading of the CLUT. This bit is
+ automatically reset: ** at the end of the transfer **
+ when the transfer is aborted by the user application
+ by setting the ABORT bit in the DMA2D_CR ** when a
+ transfer error occurs ** when the transfer has not
+ started due to a configuration error or another
+ transfer operation already on going (data transfer or
+ automatic BackGround CLUT transfer).</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CS</name>
+ <description>CLUT size These bits define the size of
+ the CLUT used for the BG. Once the CLUT transfer has
+ started, this field is read-only. The number of CLUT
+ entries is equal to CS[7:0] + 1.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>AM</name>
+ <description>Alpha mode These bits define which alpha
+ channel value to be used for the background image.
+ These bits can only be written when data transfers
+ are disabled. Once the transfer has started, they are
+ read-only. others: meaningless</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>AI</name>
+ <description>Alpha Inverted This bit inverts the
+ alpha value. Once the transfer has started, this bit
+ is read-only.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RBS</name>
+ <description>Red Blue Swap This bit allows to swap
+ the R &amp;amp; B to support BGR or ABGR color
+ formats. Once the transfer has started, this bit is
+ read-only.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALPHA</name>
+ <description>Alpha value These bits define a fixed
+ alpha channel value which can replace the original
+ alpha value or be multiplied with the original alpha
+ value according to the alpha mode selected with bits
+ AM[1: 0]. These bits can only be written when data
+ transfers are disabled. Once the transfer has
+ started, they are read-only.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_BGCOLR</name>
+ <displayName>DMA2D_BGCOLR</displayName>
+ <description>DMA2D background color
+ register</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BLUE</name>
+ <description>Blue Value These bits define the blue
+ value for the A4 or A8 mode of the background. These
+ bits can only be written when data transfers are
+ disabled. Once the transfer has started, they are
+ read-only.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>GREEN</name>
+ <description>Green Value These bits define the green
+ value for the A4 or A8 mode of the background. These
+ bits can only be written when data transfers are
+ disabled. Once the transfer has started, they are
+ read-only.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RED</name>
+ <description>Red Value These bits define the red
+ value for the A4 or A8 mode of the background. These
+ bits can only be written when data transfers are
+ disabled. Once the transfer has started, they are
+ read-only.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_FGCMAR</name>
+ <displayName>DMA2D_FGCMAR</displayName>
+ <description>DMA2D foreground CLUT memory address
+ register</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory Address Address of the data used
+ for the CLUT address dedicated to the foreground
+ image. This register can only be written when no
+ transfer is ongoing. Once the CLUT transfer has
+ started, this register is read-only. If the
+ foreground CLUT format is 32-bit, the address must be
+ 32-bit aligned.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_BGCMAR</name>
+ <displayName>DMA2D_BGCMAR</displayName>
+ <description>DMA2D background CLUT memory address
+ register</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory address Address of the data used
+ for the CLUT address dedicated to the background
+ image. This register can only be written when no
+ transfer is on going. Once the CLUT transfer has
+ started, this register is read-only. If the
+ background CLUT format is 32-bit, the address must be
+ 32-bit aligned.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_OPFCCR</name>
+ <displayName>DMA2D_OPFCCR</displayName>
+ <description>DMA2D output PFC control
+ register</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CM</name>
+ <description>Color mode These bits define the color
+ format of the output image. These bits can only be
+ written when data transfers are disabled. Once the
+ transfer has started, they are read-only. others:
+ meaningless</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>AI</name>
+ <description>Alpha Inverted This bit inverts the
+ alpha value. Once the transfer has started, this bit
+ is read-only.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RBS</name>
+ <description>Red Blue Swap This bit allows to swap
+ the R &amp;amp; B to support BGR or ABGR color
+ formats. Once the transfer has started, this bit is
+ read-only.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_OCOLR</name>
+ <displayName>DMA2D_OCOLR</displayName>
+ <description>DMA2D output color register</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>BLUE</name>
+ <description>Blue Value These bits define the blue
+ value of the output image. These bits can only be
+ written when data transfers are disabled. Once the
+ transfer has started, they are
+ read-only.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>GREEN</name>
+ <description>Green Value These bits define the green
+ value of the output image. These bits can only be
+ written when data transfers are disabled. Once the
+ transfer has started, they are
+ read-only.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RED</name>
+ <description>Red Value These bits define the red
+ value of the output image. These bits can only be
+ written when data transfers are disabled. Once the
+ transfer has started, they are
+ read-only.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ALPHA</name>
+ <description>Alpha Channel Value These bits define
+ the alpha channel of the output color. These bits can
+ only be written when data transfers are disabled.
+ Once the transfer has started, they are
+ read-only.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_OMAR</name>
+ <displayName>DMA2D_OMAR</displayName>
+ <description>DMA2D output memory address
+ register</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MA</name>
+ <description>Memory Address Address of the data used
+ for the output FIFO. These bits can only be written
+ when data transfers are disabled. Once the transfer
+ has started, they are read-only. The address
+ alignment must match the image format selected e.g. a
+ 32-bit per pixel format must be 32-bit aligned and a
+ 16-bit per pixel format must be 16-bit
+ aligned.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_OOR</name>
+ <displayName>DMA2D_OOR</displayName>
+ <description>DMA2D output offset register</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LO</name>
+ <description>Line Offset Line offset used for the
+ output (expressed in pixels). This value is used for
+ the address generation. It is added at the end of
+ each line to determine the starting address of the
+ next line. These bits can only be written when data
+ transfers are disabled. Once the transfer has
+ started, they are read-only.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>14</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_NLR</name>
+ <displayName>DMA2D_NLR</displayName>
+ <description>DMA2D number of line register</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>NL</name>
+ <description>Number of lines Number of lines of the
+ area to be transferred. These bits can only be
+ written when data transfers are disabled. Once the
+ transfer has started, they are
+ read-only.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>PL</name>
+ <description>Pixel per lines Number of pixels per
+ lines of the area to be transferred. These bits can
+ only be written when data transfers are disabled.
+ Once the transfer has started, they are read-only. If
+ any of the input image format is 4-bit per pixel,
+ pixel per lines must be even.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>14</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_LWR</name>
+ <displayName>DMA2D_LWR</displayName>
+ <description>DMA2D line watermark register</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>LW</name>
+ <description>Line watermark These bits allow to
+ configure the line watermark for interrupt
+ generation. An interrupt is raised when the last
+ pixel of the watermarked line has been transferred.
+ These bits can only be written when data transfers
+ are disabled. Once the transfer has started, they are
+ read-only.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2D_AMTCR</name>
+ <displayName>DMA2D_AMTCR</displayName>
+ <description>DMA2D AXI master timer configuration
+ register</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Enable Enables the dead time
+ functionality.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DT</name>
+ <description>Dead Time Dead time value in the AXI
+ clock cycle inserted between two consecutive accesses
+ on the AXI master port. These bits represent the
+ minimum guaranteed number of cycles between two
+ consecutive AXI accesses.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>DMAMUX2</name>
+ <description>DMAMUX</description>
+ <groupName>DMAMUX</groupName>
+ <baseAddress>0x58025800</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>DMAMUX2_OVR</name>
+ <description>DMAMUX2 overrun interrupt</description>
+ <value>128</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>DMAMUX2_C0CR</name>
+ <displayName>DMAMUX2_C0CR</displayName>
+ <description>DMAMux - DMA request line multiplexer
+ channel x control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAREQ_ID</name>
+ <description>Input DMA request line
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SOIE</name>
+ <description>Interrupt enable at synchronization
+ event overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EGE</name>
+ <description>Event generation
+ enable/disable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SE</name>
+ <description>Synchronous operating mode
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPOL</name>
+ <description>Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NBREQ</name>
+ <description>Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SYNC_ID</name>
+ <description>Synchronization input
+ selected</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_C1CR</name>
+ <displayName>DMAMUX2_C1CR</displayName>
+ <description>DMAMux - DMA request line multiplexer
+ channel x control register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAREQ_ID</name>
+ <description>Input DMA request line
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SOIE</name>
+ <description>Interrupt enable at synchronization
+ event overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EGE</name>
+ <description>Event generation
+ enable/disable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SE</name>
+ <description>Synchronous operating mode
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPOL</name>
+ <description>Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NBREQ</name>
+ <description>Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SYNC_ID</name>
+ <description>Synchronization input
+ selected</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_C2CR</name>
+ <displayName>DMAMUX2_C2CR</displayName>
+ <description>DMAMux - DMA request line multiplexer
+ channel x control register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAREQ_ID</name>
+ <description>Input DMA request line
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SOIE</name>
+ <description>Interrupt enable at synchronization
+ event overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EGE</name>
+ <description>Event generation
+ enable/disable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SE</name>
+ <description>Synchronous operating mode
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPOL</name>
+ <description>Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NBREQ</name>
+ <description>Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SYNC_ID</name>
+ <description>Synchronization input
+ selected</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_C3CR</name>
+ <displayName>DMAMUX2_C3CR</displayName>
+ <description>DMAMux - DMA request line multiplexer
+ channel x control register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAREQ_ID</name>
+ <description>Input DMA request line
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SOIE</name>
+ <description>Interrupt enable at synchronization
+ event overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EGE</name>
+ <description>Event generation
+ enable/disable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SE</name>
+ <description>Synchronous operating mode
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPOL</name>
+ <description>Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NBREQ</name>
+ <description>Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SYNC_ID</name>
+ <description>Synchronization input
+ selected</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_C4CR</name>
+ <displayName>DMAMUX2_C4CR</displayName>
+ <description>DMAMux - DMA request line multiplexer
+ channel x control register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAREQ_ID</name>
+ <description>Input DMA request line
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SOIE</name>
+ <description>Interrupt enable at synchronization
+ event overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EGE</name>
+ <description>Event generation
+ enable/disable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SE</name>
+ <description>Synchronous operating mode
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPOL</name>
+ <description>Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NBREQ</name>
+ <description>Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SYNC_ID</name>
+ <description>Synchronization input
+ selected</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_C5CR</name>
+ <displayName>DMAMUX2_C5CR</displayName>
+ <description>DMAMux - DMA request line multiplexer
+ channel x control register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAREQ_ID</name>
+ <description>Input DMA request line
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SOIE</name>
+ <description>Interrupt enable at synchronization
+ event overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EGE</name>
+ <description>Event generation
+ enable/disable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SE</name>
+ <description>Synchronous operating mode
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPOL</name>
+ <description>Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NBREQ</name>
+ <description>Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SYNC_ID</name>
+ <description>Synchronization input
+ selected</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_C6CR</name>
+ <displayName>DMAMUX2_C6CR</displayName>
+ <description>DMAMux - DMA request line multiplexer
+ channel x control register</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAREQ_ID</name>
+ <description>Input DMA request line
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SOIE</name>
+ <description>Interrupt enable at synchronization
+ event overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EGE</name>
+ <description>Event generation
+ enable/disable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SE</name>
+ <description>Synchronous operating mode
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPOL</name>
+ <description>Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NBREQ</name>
+ <description>Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SYNC_ID</name>
+ <description>Synchronization input
+ selected</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_C7CR</name>
+ <displayName>DMAMUX2_C7CR</displayName>
+ <description>DMAMux - DMA request line multiplexer
+ channel x control register</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>DMAREQ_ID</name>
+ <description>Input DMA request line
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SOIE</name>
+ <description>Interrupt enable at synchronization
+ event overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EGE</name>
+ <description>Event generation
+ enable/disable</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SE</name>
+ <description>Synchronous operating mode
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SPOL</name>
+ <description>Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NBREQ</name>
+ <description>Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>SYNC_ID</name>
+ <description>Synchronization input
+ selected</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RG0CR</name>
+ <displayName>DMAMUX2_RG0CR</displayName>
+ <description>DMAMux - DMA request generator channel x
+ control register</description>
+ <addressOffset>0x100</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SIG_ID</name>
+ <description>DMA request trigger input
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OIE</name>
+ <description>Interrupt enable at trigger event
+ overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GE</name>
+ <description>DMA request generator channel
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPOL</name>
+ <description>DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>GNBREQ</name>
+ <description>Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RG1CR</name>
+ <displayName>DMAMUX2_RG1CR</displayName>
+ <description>DMAMux - DMA request generator channel x
+ control register</description>
+ <addressOffset>0x104</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SIG_ID</name>
+ <description>DMA request trigger input
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OIE</name>
+ <description>Interrupt enable at trigger event
+ overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GE</name>
+ <description>DMA request generator channel
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPOL</name>
+ <description>DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>GNBREQ</name>
+ <description>Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RG2CR</name>
+ <displayName>DMAMUX2_RG2CR</displayName>
+ <description>DMAMux - DMA request generator channel x
+ control register</description>
+ <addressOffset>0x108</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SIG_ID</name>
+ <description>DMA request trigger input
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OIE</name>
+ <description>Interrupt enable at trigger event
+ overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GE</name>
+ <description>DMA request generator channel
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPOL</name>
+ <description>DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>GNBREQ</name>
+ <description>Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RG3CR</name>
+ <displayName>DMAMUX2_RG3CR</displayName>
+ <description>DMAMux - DMA request generator channel x
+ control register</description>
+ <addressOffset>0x10C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SIG_ID</name>
+ <description>DMA request trigger input
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OIE</name>
+ <description>Interrupt enable at trigger event
+ overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GE</name>
+ <description>DMA request generator channel
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPOL</name>
+ <description>DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>GNBREQ</name>
+ <description>Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RG4CR</name>
+ <displayName>DMAMUX2_RG4CR</displayName>
+ <description>DMAMux - DMA request generator channel x
+ control register</description>
+ <addressOffset>0x110</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SIG_ID</name>
+ <description>DMA request trigger input
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OIE</name>
+ <description>Interrupt enable at trigger event
+ overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GE</name>
+ <description>DMA request generator channel
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPOL</name>
+ <description>DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>GNBREQ</name>
+ <description>Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RG5CR</name>
+ <displayName>DMAMUX2_RG5CR</displayName>
+ <description>DMAMux - DMA request generator channel x
+ control register</description>
+ <addressOffset>0x114</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SIG_ID</name>
+ <description>DMA request trigger input
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OIE</name>
+ <description>Interrupt enable at trigger event
+ overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GE</name>
+ <description>DMA request generator channel
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPOL</name>
+ <description>DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>GNBREQ</name>
+ <description>Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RG6CR</name>
+ <displayName>DMAMUX2_RG6CR</displayName>
+ <description>DMAMux - DMA request generator channel x
+ control register</description>
+ <addressOffset>0x118</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SIG_ID</name>
+ <description>DMA request trigger input
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OIE</name>
+ <description>Interrupt enable at trigger event
+ overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GE</name>
+ <description>DMA request generator channel
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPOL</name>
+ <description>DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>GNBREQ</name>
+ <description>Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RG7CR</name>
+ <displayName>DMAMUX2_RG7CR</displayName>
+ <description>DMAMux - DMA request generator channel x
+ control register</description>
+ <addressOffset>0x11C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SIG_ID</name>
+ <description>DMA request trigger input
+ selected</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ <field>
+ <name>OIE</name>
+ <description>Interrupt enable at trigger event
+ overrun</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GE</name>
+ <description>DMA request generator channel
+ enable/disable</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GPOL</name>
+ <description>DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>GNBREQ</name>
+ <description>Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>5</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RGSR</name>
+ <displayName>DMAMUX2_RGSR</displayName>
+ <description>DMAMux - DMA request generator status
+ register</description>
+ <addressOffset>0x140</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OF</name>
+ <description>Trigger event overrun flag The flag is
+ set when a trigger event occurs on DMA request
+ generator channel x, while the DMA request generator
+ counter value is lower than GNBREQ. The flag is
+ cleared by writing 1 to the corresponding COFx bit in
+ DMAMUX_RGCFR register.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_RGCFR</name>
+ <displayName>DMAMUX2_RGCFR</displayName>
+ <description>DMAMux - DMA request generator clear flag
+ register</description>
+ <addressOffset>0x144</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>COF</name>
+ <description>Clear trigger event overrun flag Upon
+ setting, this bit clears the corresponding overrun
+ flag OFx in the DMAMUX_RGCSR register.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_CSR</name>
+ <displayName>DMAMUX2_CSR</displayName>
+ <description>DMAMUX request line multiplexer interrupt
+ channel status register</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SOF</name>
+ <description>Synchronization overrun event
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAMUX2_CFR</name>
+ <displayName>DMAMUX2_CFR</displayName>
+ <description>DMAMUX request line multiplexer interrupt
+ clear flag register</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CSOF</name>
+ <description>Clear synchronization overrun event
+ flag</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>FMC</name>
+ <description>FMC</description>
+ <groupName>FMC</groupName>
+ <baseAddress>0x52004000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>FMC</name>
+ <description>FMC global interrupt</description>
+ <value>48</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>FMC_BCR1</name>
+ <displayName>FMC_BCR1</displayName>
+ <description>This register contains the control
+ information of each memory bank, used for SRAMs, PSRAM
+ and NOR Flash memories.</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000030DB</resetValue>
+ <fields>
+ <field>
+ <name>MBKEN</name>
+ <description>Memory bank enable bit This bit enables
+ the memory bank. After reset Bank1 is enabled, all
+ others are disabled. Accessing a disabled bank causes
+ an ERROR on AXI bus.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUXEN</name>
+ <description>Address/data multiplexing enable bit
+ When this bit is set, the address and data values are
+ multiplexed on the data bus, valid only with NOR and
+ PSRAM memories:</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MTYP</name>
+ <description>Memory type These bits define the type
+ of external memory attached to the corresponding
+ memory bank:</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>Memory data bus width Defines the
+ external memory device width, valid for all type of
+ memories.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FACCEN</name>
+ <description>Flash access enable This bit enables NOR
+ Flash memory access operations.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BURSTEN</name>
+ <description>Burst enable bit This bit
+ enables/disables synchronous accesses during read
+ operations. It is valid only for synchronous memories
+ operating in Burst mode:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPOL</name>
+ <description>Wait signal polarity bit This bit
+ defines the polarity of the wait signal from memory
+ used for either in synchronous or asynchronous
+ mode:</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITCFG</name>
+ <description>Wait timing configuration The NWAIT
+ signal indicates whether the data from the memory are
+ valid or if a wait state must be inserted when
+ accessing the memory in synchronous mode. This
+ configuration bit determines if NWAIT is asserted by
+ the memory one clock cycle before the wait state or
+ during the wait state:</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WREN</name>
+ <description>Write enable bit This bit indicates
+ whether write operations are enabled/disabled in the
+ bank by the FMC:</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITEN</name>
+ <description>Wait enable bit This bit
+ enables/disables wait-state insertion via the NWAIT
+ signal when accessing the memory in synchronous
+ mode.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTMOD</name>
+ <description>Extended mode enable. This bit enables
+ the FMC to program the write timings for asynchronous
+ accesses inside the FMC_BWTR register, thus resulting
+ in different timings for read and write operations.
+ Note: When the extended mode is disabled, the FMC can
+ operate in Mode1 or Mode2 as follows: ** Mode 1 is
+ the default mode when the SRAM/PSRAM memory type is
+ selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
+ mode when the NOR memory type is selected (MTYP =
+ 0x10).</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ASYNCWAIT</name>
+ <description>Wait signal during asynchronous
+ transfers This bit enables/disables the FMC to use
+ the wait signal even during an asynchronous
+ protocol.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPSIZE</name>
+ <description>CRAM Page Size These are used for
+ Cellular RAM 1.5 which does not allow burst access to
+ cross the address boundaries between pages. When
+ these bits are configured, the FMC controller splits
+ automatically the burst access when the memory page
+ size is reached (refer to memory datasheet for page
+ size). Other configuration: reserved.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CBURSTRW</name>
+ <description>Write burst enable For PSRAM (CRAM)
+ operating in Burst mode, the bit enables synchronous
+ accesses during write operations. The enable bit for
+ synchronous read accesses is the BURSTEN bit in the
+ FMC_BCRx register.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCLKEN</name>
+ <description>Continuous Clock Enable This bit enables
+ the FMC_CLK clock output to external memory devices.
+ Note: The CCLKEN bit of the FMC_BCR2..4 registers is
+ dont care. It is only enabled through the FMC_BCR1
+ register. Bank 1 must be configured in synchronous
+ mode to generate the FMC_CLK continuous clock. If
+ CCLKEN bit is set, the FMC_CLK clock ratio is
+ specified by CLKDIV value in the FMC_BTR1 register.
+ CLKDIV in FMC_BWTR1 is dont care. If the synchronous
+ mode is used and CCLKEN bit is set, the synchronous
+ memories connected to other banks than Bank 1 are
+ clocked by the same clock (the CLKDIV value in the
+ FMC_BTR2..4 and FMC_BWTR2..4 registers for other
+ banks has no effect.)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WFDIS</name>
+ <description>Write FIFO Disable This bit disables the
+ Write FIFO used by the FMC controller. Note: The
+ WFDIS bit of the FMC_BCR2..4 registers is dont care.
+ It is only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BMAP</name>
+ <description>FMC bank mapping These bits allows
+ different to remap SDRAM bank2 or swap the FMC
+ NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
+ The BMAP bits of the FMC_BCR2..4 registers are dont
+ care. It is only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FMCEN</name>
+ <description>FMC controller Enable This bit
+ enables/disables the FMC controller. Note: The FMCEN
+ bit of the FMC_BCR2..4 registers is dont care. It is
+ only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BTR1</name>
+ <displayName>FMC_BTR1</displayName>
+ <description>This register contains the control
+ information of each memory bank, used for SRAMs, PSRAM
+ and NOR Flash memories.If the EXTMOD bit is set in the
+ FMC_BCRx register, then this register is partitioned for
+ write and read access, that is, 2 registers are
+ available: one to configure read accesses (this register)
+ and one to configure write accesses (FMC_BWTRx
+ registers).</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ADDSET</name>
+ <description>Address setup phase duration These bits
+ are written by software to define the duration of the
+ address setup phase (refer to Figure81 to Figure93),
+ used in SRAMs, ROMs and asynchronous NOR Flash: For
+ each access mode address setup phase duration, please
+ refer to the respective figure (refer to Figure81 to
+ Figure93). Note: In synchronous accesses, this value
+ is dont care. In Muxed mode or Mode D, the minimum
+ value for ADDSET is 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>Address-hold phase duration These bits
+ are written by software to define the duration of the
+ address hold phase (refer to Figure81 to Figure93),
+ used in mode D or multiplexed accesses: For each
+ access mode address-hold phase duration, please refer
+ to the respective figure (Figure81 to Figure93).
+ Note: In synchronous accesses, this value is not
+ used, the address hold phase is always 1 memory clock
+ period duration.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>Data-phase duration These bits are
+ written by software to define the duration of the
+ data phase (refer to Figure81 to Figure93), used in
+ asynchronous accesses: For each memory type and
+ access mode data-phase duration, please refer to the
+ respective figure (Figure81 to Figure93). Example:
+ Mode1, write access, DATAST=1: Data-phase duration=
+ DATAST+1 = 2 KCK_FMC clock cycles. Note: In
+ synchronous accesses, this value is dont
+ care.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>Bus turnaround phase duration These bits
+ are written by software to add a delay at the end of
+ a write-to-read or read-to write transaction. The
+ programmed bus turnaround delay is inserted between
+ an asynchronous read (in muxed or mode D) or write
+ transaction and any other asynchronous /synchronous
+ read/write from/to a static bank. If a read operation
+ is performed, the bank can be the same or a different
+ one, whereas it must be different in case of write
+ operation to the bank, except in muxed mode or mode
+ D. In some cases, whatever the programmed BUSTRUN
+ values, the bus turnaround delay is fixed as follows:
+ The bus turnaround delay is not inserted between two
+ consecutive asynchronous write transfers to the same
+ static memory bank except in muxed mode and mode D.
+ There is a bus turnaround delay of 1 FMC clock cycle
+ between: Two consecutive asynchronous read transfers
+ to the same static memory bank except for modes muxed
+ and D. An asynchronous read to an asynchronous or
+ synchronous write to any static bank or dynamic bank
+ except in modes muxed and D mode. There is a bus
+ turnaround delay of 2 FMC clock cycle between: Two
+ consecutive synchronous write operations (in Burst or
+ Single mode) to the same bank. A synchronous write
+ (burst or single) access and an asynchronous write or
+ read transfer to or from static memory bank (the bank
+ can be the same or a different one in case of a read
+ operation. Two consecutive synchronous read
+ operations (in Burst or Single mode) followed by any
+ synchronous/asynchronous read or write from/to
+ another static memory bank. There is a bus turnaround
+ delay of 3 FMC clock cycle between: Two consecutive
+ synchronous write operations (in Burst or Single
+ mode) to different static banks. A synchronous write
+ access (in Burst or Single mode) and a synchronous
+ read from the same or a different bank. The bus
+ turnaround delay allows to match the minimum time
+ between consecutive transactions (tEHEL from NEx high
+ to NEx low) and the maximum time required by the
+ memory to free the data bus after a read access
+ (tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
+ tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805;
+ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
+ &amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126.
+ ...</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>Clock divide ratio (for FMC_CLK signal)
+ These bits define the period of FMC_CLK clock output
+ signal, expressed in number of KCK_FMC cycles: In
+ asynchronous NOR Flash, SRAM or PSRAM accesses, this
+ value is dont care. Note: Refer to Section20.6.5:
+ Synchronous transactions for FMC_CLK divider ratio
+ formula)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>Data latency for synchronous memory For
+ synchronous access with read write burst mode enabled
+ these bits define the number of memory clock
+ cycles</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ACCMOD</name>
+ <description>Access mode These bits specify the
+ asynchronous access modes as shown in the timing
+ diagrams. They are taken into account only when the
+ EXTMOD bit in the FMC_BCRx register is
+ 1.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BCR2</name>
+ <displayName>FMC_BCR2</displayName>
+ <description>This register contains the control
+ information of each memory bank, used for SRAMs, PSRAM
+ and NOR Flash memories.</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000030D2</resetValue>
+ <fields>
+ <field>
+ <name>MBKEN</name>
+ <description>Memory bank enable bit This bit enables
+ the memory bank. After reset Bank1 is enabled, all
+ others are disabled. Accessing a disabled bank causes
+ an ERROR on AXI bus.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUXEN</name>
+ <description>Address/data multiplexing enable bit
+ When this bit is set, the address and data values are
+ multiplexed on the data bus, valid only with NOR and
+ PSRAM memories:</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MTYP</name>
+ <description>Memory type These bits define the type
+ of external memory attached to the corresponding
+ memory bank:</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>Memory data bus width Defines the
+ external memory device width, valid for all type of
+ memories.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FACCEN</name>
+ <description>Flash access enable This bit enables NOR
+ Flash memory access operations.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BURSTEN</name>
+ <description>Burst enable bit This bit
+ enables/disables synchronous accesses during read
+ operations. It is valid only for synchronous memories
+ operating in Burst mode:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPOL</name>
+ <description>Wait signal polarity bit This bit
+ defines the polarity of the wait signal from memory
+ used for either in synchronous or asynchronous
+ mode:</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITCFG</name>
+ <description>Wait timing configuration The NWAIT
+ signal indicates whether the data from the memory are
+ valid or if a wait state must be inserted when
+ accessing the memory in synchronous mode. This
+ configuration bit determines if NWAIT is asserted by
+ the memory one clock cycle before the wait state or
+ during the wait state:</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WREN</name>
+ <description>Write enable bit This bit indicates
+ whether write operations are enabled/disabled in the
+ bank by the FMC:</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITEN</name>
+ <description>Wait enable bit This bit
+ enables/disables wait-state insertion via the NWAIT
+ signal when accessing the memory in synchronous
+ mode.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTMOD</name>
+ <description>Extended mode enable. This bit enables
+ the FMC to program the write timings for asynchronous
+ accesses inside the FMC_BWTR register, thus resulting
+ in different timings for read and write operations.
+ Note: When the extended mode is disabled, the FMC can
+ operate in Mode1 or Mode2 as follows: ** Mode 1 is
+ the default mode when the SRAM/PSRAM memory type is
+ selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
+ mode when the NOR memory type is selected (MTYP =
+ 0x10).</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ASYNCWAIT</name>
+ <description>Wait signal during asynchronous
+ transfers This bit enables/disables the FMC to use
+ the wait signal even during an asynchronous
+ protocol.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPSIZE</name>
+ <description>CRAM Page Size These are used for
+ Cellular RAM 1.5 which does not allow burst access to
+ cross the address boundaries between pages. When
+ these bits are configured, the FMC controller splits
+ automatically the burst access when the memory page
+ size is reached (refer to memory datasheet for page
+ size). Other configuration: reserved.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CBURSTRW</name>
+ <description>Write burst enable For PSRAM (CRAM)
+ operating in Burst mode, the bit enables synchronous
+ accesses during write operations. The enable bit for
+ synchronous read accesses is the BURSTEN bit in the
+ FMC_BCRx register.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCLKEN</name>
+ <description>Continuous Clock Enable This bit enables
+ the FMC_CLK clock output to external memory devices.
+ Note: The CCLKEN bit of the FMC_BCR2..4 registers is
+ dont care. It is only enabled through the FMC_BCR1
+ register. Bank 1 must be configured in synchronous
+ mode to generate the FMC_CLK continuous clock. If
+ CCLKEN bit is set, the FMC_CLK clock ratio is
+ specified by CLKDIV value in the FMC_BTR1 register.
+ CLKDIV in FMC_BWTR1 is dont care. If the synchronous
+ mode is used and CCLKEN bit is set, the synchronous
+ memories connected to other banks than Bank 1 are
+ clocked by the same clock (the CLKDIV value in the
+ FMC_BTR2..4 and FMC_BWTR2..4 registers for other
+ banks has no effect.)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WFDIS</name>
+ <description>Write FIFO Disable This bit disables the
+ Write FIFO used by the FMC controller. Note: The
+ WFDIS bit of the FMC_BCR2..4 registers is dont care.
+ It is only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BMAP</name>
+ <description>FMC bank mapping These bits allows
+ different to remap SDRAM bank2 or swap the FMC
+ NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
+ The BMAP bits of the FMC_BCR2..4 registers are dont
+ care. It is only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FMCEN</name>
+ <description>FMC controller Enable This bit
+ enables/disables the FMC controller. Note: The FMCEN
+ bit of the FMC_BCR2..4 registers is dont care. It is
+ only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BTR2</name>
+ <displayName>FMC_BTR2</displayName>
+ <description>This register contains the control
+ information of each memory bank, used for SRAMs, PSRAM
+ and NOR Flash memories.If the EXTMOD bit is set in the
+ FMC_BCRx register, then this register is partitioned for
+ write and read access, that is, 2 registers are
+ available: one to configure read accesses (this register)
+ and one to configure write accesses (FMC_BWTRx
+ registers).</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ADDSET</name>
+ <description>Address setup phase duration These bits
+ are written by software to define the duration of the
+ address setup phase (refer to Figure81 to Figure93),
+ used in SRAMs, ROMs and asynchronous NOR Flash: For
+ each access mode address setup phase duration, please
+ refer to the respective figure (refer to Figure81 to
+ Figure93). Note: In synchronous accesses, this value
+ is dont care. In Muxed mode or Mode D, the minimum
+ value for ADDSET is 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>Address-hold phase duration These bits
+ are written by software to define the duration of the
+ address hold phase (refer to Figure81 to Figure93),
+ used in mode D or multiplexed accesses: For each
+ access mode address-hold phase duration, please refer
+ to the respective figure (Figure81 to Figure93).
+ Note: In synchronous accesses, this value is not
+ used, the address hold phase is always 1 memory clock
+ period duration.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>Data-phase duration These bits are
+ written by software to define the duration of the
+ data phase (refer to Figure81 to Figure93), used in
+ asynchronous accesses: For each memory type and
+ access mode data-phase duration, please refer to the
+ respective figure (Figure81 to Figure93). Example:
+ Mode1, write access, DATAST=1: Data-phase duration=
+ DATAST+1 = 2 KCK_FMC clock cycles. Note: In
+ synchronous accesses, this value is dont
+ care.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>Bus turnaround phase duration These bits
+ are written by software to add a delay at the end of
+ a write-to-read or read-to write transaction. The
+ programmed bus turnaround delay is inserted between
+ an asynchronous read (in muxed or mode D) or write
+ transaction and any other asynchronous /synchronous
+ read/write from/to a static bank. If a read operation
+ is performed, the bank can be the same or a different
+ one, whereas it must be different in case of write
+ operation to the bank, except in muxed mode or mode
+ D. In some cases, whatever the programmed BUSTRUN
+ values, the bus turnaround delay is fixed as follows:
+ The bus turnaround delay is not inserted between two
+ consecutive asynchronous write transfers to the same
+ static memory bank except in muxed mode and mode D.
+ There is a bus turnaround delay of 1 FMC clock cycle
+ between: Two consecutive asynchronous read transfers
+ to the same static memory bank except for modes muxed
+ and D. An asynchronous read to an asynchronous or
+ synchronous write to any static bank or dynamic bank
+ except in modes muxed and D mode. There is a bus
+ turnaround delay of 2 FMC clock cycle between: Two
+ consecutive synchronous write operations (in Burst or
+ Single mode) to the same bank. A synchronous write
+ (burst or single) access and an asynchronous write or
+ read transfer to or from static memory bank (the bank
+ can be the same or a different one in case of a read
+ operation. Two consecutive synchronous read
+ operations (in Burst or Single mode) followed by any
+ synchronous/asynchronous read or write from/to
+ another static memory bank. There is a bus turnaround
+ delay of 3 FMC clock cycle between: Two consecutive
+ synchronous write operations (in Burst or Single
+ mode) to different static banks. A synchronous write
+ access (in Burst or Single mode) and a synchronous
+ read from the same or a different bank. The bus
+ turnaround delay allows to match the minimum time
+ between consecutive transactions (tEHEL from NEx high
+ to NEx low) and the maximum time required by the
+ memory to free the data bus after a read access
+ (tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
+ tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805;
+ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
+ &amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 1.
+ ...</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>Clock divide ratio (for FMC_CLK signal)
+ These bits define the period of FMC_CLK clock output
+ signal, expressed in number of KCK_FMC cycles: In
+ asynchronous NOR Flash, SRAM or PSRAM accesses, this
+ value is dont care. Note: Refer to Section20.6.5:
+ Synchronous transactions for FMC_CLK divider ratio
+ formula)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>Data latency for synchronous memory For
+ synchronous access with read write burst mode enabled
+ these bits define the number of memory clock
+ cycles</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ACCMOD</name>
+ <description>Access mode These bits specify the
+ asynchronous access modes as shown in the timing
+ diagrams. They are taken into account only when the
+ EXTMOD bit in the FMC_BCRx register is
+ 1.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BCR3</name>
+ <displayName>FMC_BCR3</displayName>
+ <description>This register contains the control
+ information of each memory bank, used for SRAMs, PSRAM
+ and NOR Flash memories.</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000030D2</resetValue>
+ <fields>
+ <field>
+ <name>MBKEN</name>
+ <description>Memory bank enable bit This bit enables
+ the memory bank. After reset Bank1 is enabled, all
+ others are disabled. Accessing a disabled bank causes
+ an ERROR on AXI bus.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUXEN</name>
+ <description>Address/data multiplexing enable bit
+ When this bit is set, the address and data values are
+ multiplexed on the data bus, valid only with NOR and
+ PSRAM memories:</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MTYP</name>
+ <description>Memory type These bits define the type
+ of external memory attached to the corresponding
+ memory bank:</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>Memory data bus width Defines the
+ external memory device width, valid for all type of
+ memories.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FACCEN</name>
+ <description>Flash access enable This bit enables NOR
+ Flash memory access operations.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BURSTEN</name>
+ <description>Burst enable bit This bit
+ enables/disables synchronous accesses during read
+ operations. It is valid only for synchronous memories
+ operating in Burst mode:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPOL</name>
+ <description>Wait signal polarity bit This bit
+ defines the polarity of the wait signal from memory
+ used for either in synchronous or asynchronous
+ mode:</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITCFG</name>
+ <description>Wait timing configuration The NWAIT
+ signal indicates whether the data from the memory are
+ valid or if a wait state must be inserted when
+ accessing the memory in synchronous mode. This
+ configuration bit determines if NWAIT is asserted by
+ the memory one clock cycle before the wait state or
+ during the wait state:</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WREN</name>
+ <description>Write enable bit This bit indicates
+ whether write operations are enabled/disabled in the
+ bank by the FMC:</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITEN</name>
+ <description>Wait enable bit This bit
+ enables/disables wait-state insertion via the NWAIT
+ signal when accessing the memory in synchronous
+ mode.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTMOD</name>
+ <description>Extended mode enable. This bit enables
+ the FMC to program the write timings for asynchronous
+ accesses inside the FMC_BWTR register, thus resulting
+ in different timings for read and write operations.
+ Note: When the extended mode is disabled, the FMC can
+ operate in Mode1 or Mode2 as follows: ** Mode 1 is
+ the default mode when the SRAM/PSRAM memory type is
+ selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
+ mode when the NOR memory type is selected (MTYP =
+ 0x10).</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ASYNCWAIT</name>
+ <description>Wait signal during asynchronous
+ transfers This bit enables/disables the FMC to use
+ the wait signal even during an asynchronous
+ protocol.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPSIZE</name>
+ <description>CRAM Page Size These are used for
+ Cellular RAM 1.5 which does not allow burst access to
+ cross the address boundaries between pages. When
+ these bits are configured, the FMC controller splits
+ automatically the burst access when the memory page
+ size is reached (refer to memory datasheet for page
+ size). Other configuration: reserved.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CBURSTRW</name>
+ <description>Write burst enable For PSRAM (CRAM)
+ operating in Burst mode, the bit enables synchronous
+ accesses during write operations. The enable bit for
+ synchronous read accesses is the BURSTEN bit in the
+ FMC_BCRx register.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCLKEN</name>
+ <description>Continuous Clock Enable This bit enables
+ the FMC_CLK clock output to external memory devices.
+ Note: The CCLKEN bit of the FMC_BCR2..4 registers is
+ dont care. It is only enabled through the FMC_BCR1
+ register. Bank 1 must be configured in synchronous
+ mode to generate the FMC_CLK continuous clock. If
+ CCLKEN bit is set, the FMC_CLK clock ratio is
+ specified by CLKDIV value in the FMC_BTR1 register.
+ CLKDIV in FMC_BWTR1 is dont care. If the synchronous
+ mode is used and CCLKEN bit is set, the synchronous
+ memories connected to other banks than Bank 1 are
+ clocked by the same clock (the CLKDIV value in the
+ FMC_BTR2..4 and FMC_BWTR2..4 registers for other
+ banks has no effect.)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WFDIS</name>
+ <description>Write FIFO Disable This bit disables the
+ Write FIFO used by the FMC controller. Note: The
+ WFDIS bit of the FMC_BCR2..4 registers is dont care.
+ It is only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BMAP</name>
+ <description>FMC bank mapping These bits allows
+ different to remap SDRAM bank2 or swap the FMC
+ NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
+ The BMAP bits of the FMC_BCR2..4 registers are dont
+ care. It is only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FMCEN</name>
+ <description>FMC controller Enable This bit
+ enables/disables the FMC controller. Note: The FMCEN
+ bit of the FMC_BCR2..4 registers is dont care. It is
+ only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BTR3</name>
+ <displayName>FMC_BTR3</displayName>
+ <description>This register contains the control
+ information of each memory bank, used for SRAMs, PSRAM
+ and NOR Flash memories.If the EXTMOD bit is set in the
+ FMC_BCRx register, then this register is partitioned for
+ write and read access, that is, 2 registers are
+ available: one to configure read accesses (this register)
+ and one to configure write accesses (FMC_BWTRx
+ registers).</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ADDSET</name>
+ <description>Address setup phase duration These bits
+ are written by software to define the duration of the
+ address setup phase (refer to Figure81 to Figure93),
+ used in SRAMs, ROMs and asynchronous NOR Flash: For
+ each access mode address setup phase duration, please
+ refer to the respective figure (refer to Figure81 to
+ Figure93). Note: In synchronous accesses, this value
+ is dont care. In Muxed mode or Mode D, the minimum
+ value for ADDSET is 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>Address-hold phase duration These bits
+ are written by software to define the duration of the
+ address hold phase (refer to Figure81 to Figure93),
+ used in mode D or multiplexed accesses: For each
+ access mode address-hold phase duration, please refer
+ to the respective figure (Figure81 to Figure93).
+ Note: In synchronous accesses, this value is not
+ used, the address hold phase is always 1 memory clock
+ period duration.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>Data-phase duration These bits are
+ written by software to define the duration of the
+ data phase (refer to Figure81 to Figure93), used in
+ asynchronous accesses: For each memory type and
+ access mode data-phase duration, please refer to the
+ respective figure (Figure81 to Figure93). Example:
+ Mode1, write access, DATAST=1: Data-phase duration=
+ DATAST+1 = 2 KCK_FMC clock cycles. Note: In
+ synchronous accesses, this value is dont
+ care.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>Bus turnaround phase duration These bits
+ are written by software to add a delay at the end of
+ a write-to-read or read-to write transaction. The
+ programmed bus turnaround delay is inserted between
+ an asynchronous read (in muxed or mode D) or write
+ transaction and any other asynchronous /synchronous
+ read/write from/to a static bank. If a read operation
+ is performed, the bank can be the same or a different
+ one, whereas it must be different in case of write
+ operation to the bank, except in muxed mode or mode
+ D. In some cases, whatever the programmed BUSTRUN
+ values, the bus turnaround delay is fixed as follows:
+ The bus turnaround delay is not inserted between two
+ consecutive asynchronous write transfers to the same
+ static memory bank except in muxed mode and mode D.
+ There is a bus turnaround delay of 1 FMC clock cycle
+ between: Two consecutive asynchronous read transfers
+ to the same static memory bank except for modes muxed
+ and D. An asynchronous read to an asynchronous or
+ synchronous write to any static bank or dynamic bank
+ except in modes muxed and D mode. There is a bus
+ turnaround delay of 2 FMC clock cycle between: Two
+ consecutive synchronous write operations (in Burst or
+ Single mode) to the same bank. A synchronous write
+ (burst or single) access and an asynchronous write or
+ read transfer to or from static memory bank (the bank
+ can be the same or a different one in case of a read
+ operation. Two consecutive synchronous read
+ operations (in Burst or Single mode) followed by any
+ synchronous/asynchronous read or write from/to
+ another static memory bank. There is a bus turnaround
+ delay of 3 FMC clock cycle between: Two consecutive
+ synchronous write operations (in Burst or Single
+ mode) to different static banks. A synchronous write
+ access (in Burst or Single mode) and a synchronous
+ read from the same or a different bank. The bus
+ turnaround delay allows to match the minimum time
+ between consecutive transactions (tEHEL from NEx high
+ to NEx low) and the maximum time required by the
+ memory to free the data bus after a read access
+ (tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
+ tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805;
+ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
+ &amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1.
+ ...</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>Clock divide ratio (for FMC_CLK signal)
+ These bits define the period of FMC_CLK clock output
+ signal, expressed in number of KCK_FMC cycles: In
+ asynchronous NOR Flash, SRAM or PSRAM accesses, this
+ value is dont care. Note: Refer to Section20.6.5:
+ Synchronous transactions for FMC_CLK divider ratio
+ formula)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>Data latency for synchronous memory For
+ synchronous access with read write burst mode enabled
+ these bits define the number of memory clock
+ cycles</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ACCMOD</name>
+ <description>Access mode These bits specify the
+ asynchronous access modes as shown in the timing
+ diagrams. They are taken into account only when the
+ EXTMOD bit in the FMC_BCRx register is
+ 1.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BCR4</name>
+ <displayName>FMC_BCR4</displayName>
+ <description>This register contains the control
+ information of each memory bank, used for SRAMs, PSRAM
+ and NOR Flash memories.</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000030D2</resetValue>
+ <fields>
+ <field>
+ <name>MBKEN</name>
+ <description>Memory bank enable bit This bit enables
+ the memory bank. After reset Bank1 is enabled, all
+ others are disabled. Accessing a disabled bank causes
+ an ERROR on AXI bus.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MUXEN</name>
+ <description>Address/data multiplexing enable bit
+ When this bit is set, the address and data values are
+ multiplexed on the data bus, valid only with NOR and
+ PSRAM memories:</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MTYP</name>
+ <description>Memory type These bits define the type
+ of external memory attached to the corresponding
+ memory bank:</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>Memory data bus width Defines the
+ external memory device width, valid for all type of
+ memories.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FACCEN</name>
+ <description>Flash access enable This bit enables NOR
+ Flash memory access operations.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BURSTEN</name>
+ <description>Burst enable bit This bit
+ enables/disables synchronous accesses during read
+ operations. It is valid only for synchronous memories
+ operating in Burst mode:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITPOL</name>
+ <description>Wait signal polarity bit This bit
+ defines the polarity of the wait signal from memory
+ used for either in synchronous or asynchronous
+ mode:</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITCFG</name>
+ <description>Wait timing configuration The NWAIT
+ signal indicates whether the data from the memory are
+ valid or if a wait state must be inserted when
+ accessing the memory in synchronous mode. This
+ configuration bit determines if NWAIT is asserted by
+ the memory one clock cycle before the wait state or
+ during the wait state:</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WREN</name>
+ <description>Write enable bit This bit indicates
+ whether write operations are enabled/disabled in the
+ bank by the FMC:</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WAITEN</name>
+ <description>Wait enable bit This bit
+ enables/disables wait-state insertion via the NWAIT
+ signal when accessing the memory in synchronous
+ mode.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>EXTMOD</name>
+ <description>Extended mode enable. This bit enables
+ the FMC to program the write timings for asynchronous
+ accesses inside the FMC_BWTR register, thus resulting
+ in different timings for read and write operations.
+ Note: When the extended mode is disabled, the FMC can
+ operate in Mode1 or Mode2 as follows: ** Mode 1 is
+ the default mode when the SRAM/PSRAM memory type is
+ selected (MTYP =0x0 or 0x01) ** Mode 2 is the default
+ mode when the NOR memory type is selected (MTYP =
+ 0x10).</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ASYNCWAIT</name>
+ <description>Wait signal during asynchronous
+ transfers This bit enables/disables the FMC to use
+ the wait signal even during an asynchronous
+ protocol.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CPSIZE</name>
+ <description>CRAM Page Size These are used for
+ Cellular RAM 1.5 which does not allow burst access to
+ cross the address boundaries between pages. When
+ these bits are configured, the FMC controller splits
+ automatically the burst access when the memory page
+ size is reached (refer to memory datasheet for page
+ size). Other configuration: reserved.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CBURSTRW</name>
+ <description>Write burst enable For PSRAM (CRAM)
+ operating in Burst mode, the bit enables synchronous
+ accesses during write operations. The enable bit for
+ synchronous read accesses is the BURSTEN bit in the
+ FMC_BCRx register.</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CCLKEN</name>
+ <description>Continuous Clock Enable This bit enables
+ the FMC_CLK clock output to external memory devices.
+ Note: The CCLKEN bit of the FMC_BCR2..4 registers is
+ dont care. It is only enabled through the FMC_BCR1
+ register. Bank 1 must be configured in synchronous
+ mode to generate the FMC_CLK continuous clock. If
+ CCLKEN bit is set, the FMC_CLK clock ratio is
+ specified by CLKDIV value in the FMC_BTR1 register.
+ CLKDIV in FMC_BWTR1 is dont care. If the synchronous
+ mode is used and CCLKEN bit is set, the synchronous
+ memories connected to other banks than Bank 1 are
+ clocked by the same clock (the CLKDIV value in the
+ FMC_BTR2..4 and FMC_BWTR2..4 registers for other
+ banks has no effect.)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WFDIS</name>
+ <description>Write FIFO Disable This bit disables the
+ Write FIFO used by the FMC controller. Note: The
+ WFDIS bit of the FMC_BCR2..4 registers is dont care.
+ It is only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BMAP</name>
+ <description>FMC bank mapping These bits allows
+ different to remap SDRAM bank2 or swap the FMC
+ NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note:
+ The BMAP bits of the FMC_BCR2..4 registers are dont
+ care. It is only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>FMCEN</name>
+ <description>FMC controller Enable This bit
+ enables/disables the FMC controller. Note: The FMCEN
+ bit of the FMC_BCR2..4 registers is dont care. It is
+ only enabled through the FMC_BCR1
+ register.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BTR4</name>
+ <displayName>FMC_BTR4</displayName>
+ <description>This register contains the control
+ information of each memory bank, used for SRAMs, PSRAM
+ and NOR Flash memories.If the EXTMOD bit is set in the
+ FMC_BCRx register, then this register is partitioned for
+ write and read access, that is, 2 registers are
+ available: one to configure read accesses (this register)
+ and one to configure write accesses (FMC_BWTRx
+ registers).</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ADDSET</name>
+ <description>Address setup phase duration These bits
+ are written by software to define the duration of the
+ address setup phase (refer to Figure81 to Figure93),
+ used in SRAMs, ROMs and asynchronous NOR Flash: For
+ each access mode address setup phase duration, please
+ refer to the respective figure (refer to Figure81 to
+ Figure93). Note: In synchronous accesses, this value
+ is dont care. In Muxed mode or Mode D, the minimum
+ value for ADDSET is 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>Address-hold phase duration These bits
+ are written by software to define the duration of the
+ address hold phase (refer to Figure81 to Figure93),
+ used in mode D or multiplexed accesses: For each
+ access mode address-hold phase duration, please refer
+ to the respective figure (Figure81 to Figure93).
+ Note: In synchronous accesses, this value is not
+ used, the address hold phase is always 1 memory clock
+ period duration.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>Data-phase duration These bits are
+ written by software to define the duration of the
+ data phase (refer to Figure81 to Figure93), used in
+ asynchronous accesses: For each memory type and
+ access mode data-phase duration, please refer to the
+ respective figure (Figure81 to Figure93). Example:
+ Mode1, write access, DATAST=1: Data-phase duration=
+ DATAST+1 = 2 KCK_FMC clock cycles. Note: In
+ synchronous accesses, this value is dont
+ care.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>Bus turnaround phase duration These bits
+ are written by software to add a delay at the end of
+ a write-to-read or read-to write transaction. The
+ programmed bus turnaround delay is inserted between
+ an asynchronous read (in muxed or mode D) or write
+ transaction and any other asynchronous /synchronous
+ read/write from/to a static bank. If a read operation
+ is performed, the bank can be the same or a different
+ one, whereas it must be different in case of write
+ operation to the bank, except in muxed mode or mode
+ D. In some cases, whatever the programmed BUSTRUN
+ values, the bus turnaround delay is fixed as follows:
+ The bus turnaround delay is not inserted between two
+ consecutive asynchronous write transfers to the same
+ static memory bank except in muxed mode and mode D.
+ There is a bus turnaround delay of 1 FMC clock cycle
+ between: Two consecutive asynchronous read transfers
+ to the same static memory bank except for modes muxed
+ and D. An asynchronous read to an asynchronous or
+ synchronous write to any static bank or dynamic bank
+ except in modes muxed and D mode. There is a bus
+ turnaround delay of 2 FMC clock cycle between: Two
+ consecutive synchronous write operations (in Burst or
+ Single mode) to the same bank. A synchronous write
+ (burst or single) access and an asynchronous write or
+ read transfer to or from static memory bank (the bank
+ can be the same or a different one in case of a read
+ operation. Two consecutive synchronous read
+ operations (in Burst or Single mode) followed by any
+ synchronous/asynchronous read or write from/to
+ another static memory bank. There is a bus turnaround
+ delay of 3 FMC clock cycle between: Two consecutive
+ synchronous write operations (in Burst or Single
+ mode) to different static banks. A synchronous write
+ access (in Burst or Single mode) and a synchronous
+ read from the same or a different bank. The bus
+ turnaround delay allows to match the minimum time
+ between consecutive transactions (tEHEL from NEx high
+ to NEx low) and the maximum time required by the
+ memory to free the data bus after a read access
+ (tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
+ tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805;
+ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period
+ &amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1.
+ ...</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>Clock divide ratio (for FMC_CLK signal)
+ These bits define the period of FMC_CLK clock output
+ signal, expressed in number of KCK_FMC cycles: In
+ asynchronous NOR Flash, SRAM or PSRAM accesses, this
+ value is dont care. Note: Refer to Section20.6.5:
+ Synchronous transactions for FMC_CLK divider ratio
+ formula)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATLAT</name>
+ <description>Data latency for synchronous memory For
+ synchronous access with read write burst mode enabled
+ these bits define the number of memory clock
+ cycles</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ACCMOD</name>
+ <description>Access mode These bits specify the
+ asynchronous access modes as shown in the timing
+ diagrams. They are taken into account only when the
+ EXTMOD bit in the FMC_BCRx register is
+ 1.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_PCR</name>
+ <displayName>FMC_PCR</displayName>
+ <description>NAND Flash control registers</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000018</resetValue>
+ <fields>
+ <field>
+ <name>PWAITEN</name>
+ <description>Wait feature enable bit. This bit
+ enables the Wait feature for the NAND Flash memory
+ bank:</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PBKEN</name>
+ <description>NAND Flash memory bank enable bit. This
+ bit enables the memory bank. Accessing a disabled
+ memory bank causes an ERROR on AXI bus</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PWID</name>
+ <description>Data bus width. These bits define the
+ external memory device width.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>ECCEN</name>
+ <description>ECC computation logic enable
+ bit</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCLR</name>
+ <description>CLE to RE delay. These bits set time
+ from CLE low to RE low in number of KCK_FMC clock
+ cycles. The time is give by the following formula:
+ t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is
+ the KCK_FMC clock period Note: Set is MEMSET or
+ ATTSET according to the addressed
+ space.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TAR</name>
+ <description>ALE to RE delay. These bits set time
+ from ALE low to RE low in number of KCK_FMC clock
+ cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC
+ where TKCK_FMC is the FMC clock period Note: Set is
+ MEMSET or ATTSET according to the addressed
+ space.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ECCPS</name>
+ <description>ECC page size. These bits define the
+ page size for the extended ECC:</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_SR</name>
+ <displayName>FMC_SR</displayName>
+ <description>This register contains information about the
+ FIFO status and interrupt. The FMC features a FIFO that
+ is used when writing to memories to transfer up to 16
+ words of data.This is used to quickly write to the FIFO
+ and free the AXI bus for transactions to peripherals
+ other than the FMC, while the FMC is draining its FIFO
+ into the memory. One of these register bits indicates the
+ status of the FIFO, for ECC purposes.The ECC is
+ calculated while the data are written to the memory. To
+ read the correct ECC, the software must consequently wait
+ until the FIFO is empty.</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000040</resetValue>
+ <fields>
+ <field>
+ <name>IRS</name>
+ <description>Interrupt rising edge status The flag is
+ set by hardware and reset by software. Note: If this
+ bit is written by software to 1 it will be
+ set.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ILS</name>
+ <description>Interrupt high-level status The flag is
+ set by hardware and reset by software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IFS</name>
+ <description>Interrupt falling edge status The flag
+ is set by hardware and reset by software. Note: If
+ this bit is written by software to 1 it will be
+ set.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IREN</name>
+ <description>Interrupt rising edge detection enable
+ bit</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ILEN</name>
+ <description>Interrupt high-level detection enable
+ bit</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>IFEN</name>
+ <description>Interrupt falling edge detection enable
+ bit</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FEMPT</name>
+ <description>FIFO empty. Read-only bit that provides
+ the status of the FIFO</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_PMEM</name>
+ <displayName>FMC_PMEM</displayName>
+ <description>The FMC_PMEM read/write register contains
+ the timing information for NAND Flash memory bank. This
+ information is used to access either the common memory
+ space of the NAND Flash for command, address write access
+ and data read/write access.</description>
+ <addressOffset>0x88</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>MEMSET</name>
+ <description>Common memory x setup time These bits
+ define the number of KCK_FMC (+1) clock cycles to set
+ up the address before the command assertion (NWE,
+ NOE), for NAND Flash read or write access to common
+ memory space:</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMWAIT</name>
+ <description>Common memory wait time These bits
+ define the minimum number of KCK_FMC (+1) clock
+ cycles to assert the command (NWE, NOE), for NAND
+ Flash read or write access to common memory space.
+ The duration of command assertion is extended if the
+ wait signal (NWAIT) is active (low) at the end of the
+ programmed value of KCK_FMC:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMHOLD</name>
+ <description>Common memory hold time These bits
+ define the number of KCK_FMC clock cycles for write
+ accesses and KCK_FMC+1 clock cycles for read accesses
+ during which the address is held (and data for write
+ accesses) after the command is de-asserted (NWE,
+ NOE), for NAND Flash read or write access to common
+ memory space:</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MEMHIZ</name>
+ <description>Common memory x data bus Hi-Z time These
+ bits define the number of KCK_FMC clock cycles during
+ which the data bus is kept Hi-Z after the start of a
+ NAND Flash write access to common memory space. This
+ is only valid for write transactions:</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_PATT</name>
+ <displayName>FMC_PATT</displayName>
+ <description>The FMC_PATT read/write register contains
+ the timing information for NAND Flash memory bank. It is
+ used for 8-bit accesses to the attribute memory space of
+ the NAND Flash for the last address write access if the
+ timing must differ from that of previous accesses (for
+ Ready/Busy management, refer to Section20.8.5: NAND Flash
+ prewait feature).</description>
+ <addressOffset>0x8C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xFCFCFCFC</resetValue>
+ <fields>
+ <field>
+ <name>ATTSET</name>
+ <description>Attribute memory setup time These bits
+ define the number of KCK_FMC (+1) clock cycles to set
+ up address before the command assertion (NWE, NOE),
+ for NAND Flash read or write access to attribute
+ memory space:</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTWAIT</name>
+ <description>Attribute memory wait time These bits
+ define the minimum number of x KCK_FMC (+1) clock
+ cycles to assert the command (NWE, NOE), for NAND
+ Flash read or write access to attribute memory space.
+ The duration for command assertion is extended if the
+ wait signal (NWAIT) is active (low) at the end of the
+ programmed value of KCK_FMC:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTHOLD</name>
+ <description>Attribute memory hold time These bits
+ define the number of KCK_FMC clock cycles during
+ which the address is held (and data for write access)
+ after the command de-assertion (NWE, NOE), for NAND
+ Flash read or write access to attribute memory
+ space:</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ATTHIZ</name>
+ <description>Attribute memory data bus Hi-Z time
+ These bits define the number of KCK_FMC clock cycles
+ during which the data bus is kept in Hi-Z after the
+ start of a NAND Flash write access to attribute
+ memory space on socket. Only valid for writ
+ transaction:</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_ECCR</name>
+ <displayName>FMC_ECCR</displayName>
+ <description>This register contain the current error
+ correction code value computed by the ECC computation
+ modules of the FMC NAND controller. When the CPU
+ reads/writes the data from a NAND Flash memory page at
+ the correct address (refer to Section20.8.6: Computation
+ of the error correction code (ECC) in NAND Flash memory),
+ the data read/written from/to the NAND Flash memory are
+ processed automatically by the ECC computation module.
+ When X bytes have been read (according to the ECCPS field
+ in the FMC_PCR registers), the CPU must read the computed
+ ECC value from the FMC_ECC registers. It then verifies if
+ these computed parity data are the same as the parity
+ value recorded in the spare area, to determine whether a
+ page is valid, and, to correct it otherwise. The FMC_ECCR
+ register should be cleared after being read by setting
+ the ECCEN bit to 0. To compute a new data block, the
+ ECCEN bit must be set to 1.</description>
+ <addressOffset>0x94</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ECC</name>
+ <description>ECC result This field contains the value
+ computed by the ECC computation logic. Table167
+ describes the contents of these bit
+ fields.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BWTR1</name>
+ <displayName>FMC_BWTR1</displayName>
+ <description>This register contains the control
+ information of each memory bank. It is used for SRAMs,
+ PSRAMs and NOR Flash memories. When the EXTMOD bit is set
+ in the FMC_BCRx register, then this register is active
+ for write access.</description>
+ <addressOffset>0x104</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ADDSET</name>
+ <description>Address setup phase duration. These bits
+ are written by software to define the duration of the
+ address setup phase in KCK_FMC cycles (refer to
+ Figure81 to Figure93), used in asynchronous accesses:
+ ... Note: In synchronous accesses, this value is not
+ used, the address setup phase is always 1 Flash clock
+ period duration. In muxed mode, the minimum ADDSET
+ value is 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>Address-hold phase duration. These bits
+ are written by software to define the duration of the
+ address hold phase (refer to Figure81 to Figure93),
+ used in asynchronous multiplexed accesses: ... Note:
+ In synchronous NOR Flash accesses, this value is not
+ used, the address hold phase is always 1 Flash clock
+ period duration.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>Data-phase duration. These bits are
+ written by software to define the duration of the
+ data phase (refer to Figure81 to Figure93), used in
+ asynchronous SRAM, PSRAM and NOR Flash memory
+ accesses:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>Bus turnaround phase duration These bits
+ are written by software to add a delay at the end of
+ a write transaction to match the minimum time between
+ consecutive transactions (tEHEL from ENx high to ENx
+ low): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
+ tEHELmin. The programmed bus turnaround delay is
+ inserted between a an asynchronous write transfer and
+ any other asynchronous /synchronous read or write
+ transfer to or from a static bank. If a read
+ operation is performed, the bank can be the same or a
+ different one, whereas it must be different in case
+ of write operation to the bank, except in muxed mode
+ or mode D. In some cases, whatever the programmed
+ BUSTRUN values, the bus turnaround delay is fixed as
+ follows: The bus turnaround delay is not inserted
+ between two consecutive asynchronous write transfers
+ to the same static memory bank except for muxed mode
+ and mode D. There is a bus turnaround delay of 2 FMC
+ clock cycle between: Two consecutive synchronous
+ write operations (in Burst or Single mode) to the
+ same bank A synchronous write transfer ((in Burst or
+ Single mode) and an asynchronous write or read
+ transfer to or from static memory bank. There is a
+ bus turnaround delay of 3 FMC clock cycle between:
+ Two consecutive synchronous write operations (in
+ Burst or Single mode) to different static banks. A
+ synchronous write transfer (in Burst or Single mode)
+ and a synchronous read from the same or a different
+ bank. ...</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ACCMOD</name>
+ <description>Access mode. These bits specify the
+ asynchronous access modes as shown in the next timing
+ diagrams.These bits are taken into account only when
+ the EXTMOD bit in the FMC_BCRx register is
+ 1.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BWTR2</name>
+ <displayName>FMC_BWTR2</displayName>
+ <description>This register contains the control
+ information of each memory bank. It is used for SRAMs,
+ PSRAMs and NOR Flash memories. When the EXTMOD bit is set
+ in the FMC_BCRx register, then this register is active
+ for write access.</description>
+ <addressOffset>0x10C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ADDSET</name>
+ <description>Address setup phase duration. These bits
+ are written by software to define the duration of the
+ address setup phase in KCK_FMC cycles (refer to
+ Figure81 to Figure93), used in asynchronous accesses:
+ ... Note: In synchronous accesses, this value is not
+ used, the address setup phase is always 1 Flash clock
+ period duration. In muxed mode, the minimum ADDSET
+ value is 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>Address-hold phase duration. These bits
+ are written by software to define the duration of the
+ address hold phase (refer to Figure81 to Figure93),
+ used in asynchronous multiplexed accesses: ... Note:
+ In synchronous NOR Flash accesses, this value is not
+ used, the address hold phase is always 1 Flash clock
+ period duration.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>Data-phase duration. These bits are
+ written by software to define the duration of the
+ data phase (refer to Figure81 to Figure93), used in
+ asynchronous SRAM, PSRAM and NOR Flash memory
+ accesses:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>Bus turnaround phase duration These bits
+ are written by software to add a delay at the end of
+ a write transaction to match the minimum time between
+ consecutive transactions (tEHEL from ENx high to ENx
+ low): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
+ tEHELmin. The programmed bus turnaround delay is
+ inserted between a an asynchronous write transfer and
+ any other asynchronous /synchronous read or write
+ transfer to or from a static bank. If a read
+ operation is performed, the bank can be the same or a
+ different one, whereas it must be different in case
+ of write operation to the bank, except in muxed mode
+ or mode D. In some cases, whatever the programmed
+ BUSTRUN values, the bus turnaround delay is fixed as
+ follows: The bus turnaround delay is not inserted
+ between two consecutive asynchronous write transfers
+ to the same static memory bank except for muxed mode
+ and mode D. There is a bus turnaround delay of 2 FMC
+ clock cycle between: Two consecutive synchronous
+ write operations (in Burst or Single mode) to the
+ same bank A synchronous write transfer ((in Burst or
+ Single mode) and an asynchronous write or read
+ transfer to or from static memory bank. There is a
+ bus turnaround delay of 3 FMC clock cycle between:
+ Two consecutive synchronous write operations (in
+ Burst or Single mode) to different static banks. A
+ synchronous write transfer (in Burst or Single mode)
+ and a synchronous read from the same or a different
+ bank. ...</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ACCMOD</name>
+ <description>Access mode. These bits specify the
+ asynchronous access modes as shown in the next timing
+ diagrams.These bits are taken into account only when
+ the EXTMOD bit in the FMC_BCRx register is
+ 1.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BWTR3</name>
+ <displayName>FMC_BWTR3</displayName>
+ <description>This register contains the control
+ information of each memory bank. It is used for SRAMs,
+ PSRAMs and NOR Flash memories. When the EXTMOD bit is set
+ in the FMC_BCRx register, then this register is active
+ for write access.</description>
+ <addressOffset>0x114</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ADDSET</name>
+ <description>Address setup phase duration. These bits
+ are written by software to define the duration of the
+ address setup phase in KCK_FMC cycles (refer to
+ Figure81 to Figure93), used in asynchronous accesses:
+ ... Note: In synchronous accesses, this value is not
+ used, the address setup phase is always 1 Flash clock
+ period duration. In muxed mode, the minimum ADDSET
+ value is 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>Address-hold phase duration. These bits
+ are written by software to define the duration of the
+ address hold phase (refer to Figure81 to Figure93),
+ used in asynchronous multiplexed accesses: ... Note:
+ In synchronous NOR Flash accesses, this value is not
+ used, the address hold phase is always 1 Flash clock
+ period duration.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>Data-phase duration. These bits are
+ written by software to define the duration of the
+ data phase (refer to Figure81 to Figure93), used in
+ asynchronous SRAM, PSRAM and NOR Flash memory
+ accesses:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>Bus turnaround phase duration These bits
+ are written by software to add a delay at the end of
+ a write transaction to match the minimum time between
+ consecutive transactions (tEHEL from ENx high to ENx
+ low): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
+ tEHELmin. The programmed bus turnaround delay is
+ inserted between a an asynchronous write transfer and
+ any other asynchronous /synchronous read or write
+ transfer to or from a static bank. If a read
+ operation is performed, the bank can be the same or a
+ different one, whereas it must be different in case
+ of write operation to the bank, except in muxed mode
+ or mode D. In some cases, whatever the programmed
+ BUSTRUN values, the bus turnaround delay is fixed as
+ follows: The bus turnaround delay is not inserted
+ between two consecutive asynchronous write transfers
+ to the same static memory bank except for muxed mode
+ and mode D. There is a bus turnaround delay of 2 FMC
+ clock cycle between: Two consecutive synchronous
+ write operations (in Burst or Single mode) to the
+ same bank A synchronous write transfer ((in Burst or
+ Single mode) and an asynchronous write or read
+ transfer to or from static memory bank. There is a
+ bus turnaround delay of 3 FMC clock cycle between:
+ Two consecutive synchronous write operations (in
+ Burst or Single mode) to different static banks. A
+ synchronous write transfer (in Burst or Single mode)
+ and a synchronous read from the same or a different
+ bank. ...</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ACCMOD</name>
+ <description>Access mode. These bits specify the
+ asynchronous access modes as shown in the next timing
+ diagrams.These bits are taken into account only when
+ the EXTMOD bit in the FMC_BCRx register is
+ 1.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_BWTR4</name>
+ <displayName>FMC_BWTR4</displayName>
+ <description>This register contains the control
+ information of each memory bank. It is used for SRAMs,
+ PSRAMs and NOR Flash memories. When the EXTMOD bit is set
+ in the FMC_BCRx register, then this register is active
+ for write access.</description>
+ <addressOffset>0x11C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>ADDSET</name>
+ <description>Address setup phase duration. These bits
+ are written by software to define the duration of the
+ address setup phase in KCK_FMC cycles (refer to
+ Figure81 to Figure93), used in asynchronous accesses:
+ ... Note: In synchronous accesses, this value is not
+ used, the address setup phase is always 1 Flash clock
+ period duration. In muxed mode, the minimum ADDSET
+ value is 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ADDHLD</name>
+ <description>Address-hold phase duration. These bits
+ are written by software to define the duration of the
+ address hold phase (refer to Figure81 to Figure93),
+ used in asynchronous multiplexed accesses: ... Note:
+ In synchronous NOR Flash accesses, this value is not
+ used, the address hold phase is always 1 Flash clock
+ period duration.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>DATAST</name>
+ <description>Data-phase duration. These bits are
+ written by software to define the duration of the
+ data phase (refer to Figure81 to Figure93), used in
+ asynchronous SRAM, PSRAM and NOR Flash memory
+ accesses:</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>BUSTURN</name>
+ <description>Bus turnaround phase duration These bits
+ are written by software to add a delay at the end of
+ a write transaction to match the minimum time between
+ consecutive transactions (tEHEL from ENx high to ENx
+ low): (BUSTRUN + 1) KCK_FMC period &amp;#8805;
+ tEHELmin. The programmed bus turnaround delay is
+ inserted between a an asynchronous write transfer and
+ any other asynchronous /synchronous read or write
+ transfer to or from a static bank. If a read
+ operation is performed, the bank can be the same or a
+ different one, whereas it must be different in case
+ of write operation to the bank, except in muxed mode
+ or mode D. In some cases, whatever the programmed
+ BUSTRUN values, the bus turnaround delay is fixed as
+ follows: The bus turnaround delay is not inserted
+ between two consecutive asynchronous write transfers
+ to the same static memory bank except for muxed mode
+ and mode D. There is a bus turnaround delay of 2 FMC
+ clock cycle between: Two consecutive synchronous
+ write operations (in Burst or Single mode) to the
+ same bank A synchronous write transfer ((in Burst or
+ Single mode) and an asynchronous write or read
+ transfer to or from static memory bank. There is a
+ bus turnaround delay of 3 FMC clock cycle between:
+ Two consecutive synchronous write operations (in
+ Burst or Single mode) to different static banks. A
+ synchronous write transfer (in Burst or Single mode)
+ and a synchronous read from the same or a different
+ bank. ...</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ACCMOD</name>
+ <description>Access mode. These bits specify the
+ asynchronous access modes as shown in the next timing
+ diagrams.These bits are taken into account only when
+ the EXTMOD bit in the FMC_BCRx register is
+ 1.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_SDCR1</name>
+ <displayName>FMC_SDCR1</displayName>
+ <description>This register contains the control
+ parameters for each SDRAM memory bank</description>
+ <addressOffset>0x140</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000002D0</resetValue>
+ <fields>
+ <field>
+ <name>NC</name>
+ <description>Number of column address bits These bits
+ define the number of bits of a column
+ address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NR</name>
+ <description>Number of row address bits These bits
+ define the number of bits of a row
+ address.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>Memory data bus width. These bits define
+ the memory device width.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NB</name>
+ <description>Number of internal banks This bit sets
+ the number of internal banks.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAS</name>
+ <description>CAS Latency This bits sets the SDRAM CAS
+ latency in number of memory clock
+ cycles</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>WP</name>
+ <description>Write protection This bit enables write
+ mode access to the SDRAM bank.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDCLK</name>
+ <description>SDRAM clock configuration These bits
+ define the SDRAM clock period for both SDRAM banks
+ and allow disabling the clock before changing the
+ frequency. In this case the SDRAM must be
+ re-initialized. Note: The corresponding bits in the
+ FMC_SDCR2 register is read only.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>RBURST</name>
+ <description>Burst read This bit enables burst read
+ mode. The SDRAM controller anticipates the next read
+ commands during the CAS latency and stores data in
+ the Read FIFO. Note: The corresponding bit in the
+ FMC_SDCR2 register is read only.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RPIPE</name>
+ <description>Read pipe These bits define the delay,
+ in KCK_FMC clock cycles, for reading data after CAS
+ latency. Note: The corresponding bits in the
+ FMC_SDCR2 register is read only.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_SDCR2</name>
+ <displayName>FMC_SDCR2</displayName>
+ <description>This register contains the control
+ parameters for each SDRAM memory bank</description>
+ <addressOffset>0x144</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x000002D0</resetValue>
+ <fields>
+ <field>
+ <name>NC</name>
+ <description>Number of column address bits These bits
+ define the number of bits of a column
+ address.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NR</name>
+ <description>Number of row address bits These bits
+ define the number of bits of a row
+ address.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MWID</name>
+ <description>Memory data bus width. These bits define
+ the memory device width.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>NB</name>
+ <description>Number of internal banks This bit sets
+ the number of internal banks.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CAS</name>
+ <description>CAS Latency This bits sets the SDRAM CAS
+ latency in number of memory clock
+ cycles</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>WP</name>
+ <description>Write protection This bit enables write
+ mode access to the SDRAM bank.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SDCLK</name>
+ <description>SDRAM clock configuration These bits
+ define the SDRAM clock period for both SDRAM banks
+ and allow disabling the clock before changing the
+ frequency. In this case the SDRAM must be
+ re-initialized. Note: The corresponding bits in the
+ FMC_SDCR2 register is read only.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>RBURST</name>
+ <description>Burst read This bit enables burst read
+ mode. The SDRAM controller anticipates the next read
+ commands during the CAS latency and stores data in
+ the Read FIFO. Note: The corresponding bit in the
+ FMC_SDCR2 register is read only.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RPIPE</name>
+ <description>Read pipe These bits define the delay,
+ in KCK_FMC clock cycles, for reading data after CAS
+ latency. Note: The corresponding bits in the
+ FMC_SDCR2 register is read only.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_SDTR1</name>
+ <displayName>FMC_SDTR1</displayName>
+ <description>This register contains the timing parameters
+ of each SDRAM bank</description>
+ <addressOffset>0x148</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>TMRD</name>
+ <description>Load Mode Register to Active These bits
+ define the delay between a Load Mode Register command
+ and an Active or Refresh command in number of memory
+ clock cycles. ....</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TXSR</name>
+ <description>Exit Self-refresh delay These bits
+ define the delay from releasing the Self-refresh
+ command to issuing the Activate command in number of
+ memory clock cycles. .... Note: If two SDRAM devices
+ are used, the FMC_SDTR1 and FMC_SDTR2 must be
+ programmed with the same TXSR timing corresponding to
+ the slowest SDRAM device.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TRAS</name>
+ <description>Self refresh time These bits define the
+ minimum Self-refresh period in number of memory clock
+ cycles. ....</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TRC</name>
+ <description>Row cycle delay These bits define the
+ delay between the Refresh command and the Activate
+ command, as well as the delay between two consecutive
+ Refresh commands. It is expressed in number of memory
+ clock cycles. The TRC timing is only configured in
+ the FMC_SDTR1 register. If two SDRAM devices are
+ used, the TRC must be programmed with the timings of
+ the slowest device. .... Note: TRC must match the TRC
+ and TRFC (Auto Refresh period) timings defined in the
+ SDRAM device datasheet. Note: The corresponding bits
+ in the FMC_SDTR2 register are dont
+ care.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TWR</name>
+ <description>Recovery delay These bits define the
+ delay between a Write and a Precharge command in
+ number of memory clock cycles. .... Note: TWR must be
+ programmed to match the write recovery time (tWR)
+ defined in the SDRAM datasheet, and to guarantee
+ that: TWR &amp;#8805; TRAS - TRCD and TWR
+ &amp;#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles,
+ TRCD= 2 cycles. So, TWR &amp;gt;= 2 cycles. TWR must
+ be programmed to 0x1. If two SDRAM devices are used,
+ the FMC_SDTR1 and FMC_SDTR2 must be programmed with
+ the same TWR timing corresponding to the slowest
+ SDRAM device.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TRP</name>
+ <description>Row precharge delay These bits define
+ the delay between a Precharge command and another
+ command in number of memory clock cycles. The TRP
+ timing is only configured in the FMC_SDTR1 register.
+ If two SDRAM devices are used, the TRP must be
+ programmed with the timing of the slowest device.
+ .... Note: The corresponding bits in the FMC_SDTR2
+ register are dont care.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TRCD</name>
+ <description>Row to column delay These bits define
+ the delay between the Activate command and a
+ Read/Write command in number of memory clock cycles.
+ ....</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_SDTR2</name>
+ <displayName>FMC_SDTR2</displayName>
+ <description>This register contains the timing parameters
+ of each SDRAM bank</description>
+ <addressOffset>0x14C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0FFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>TMRD</name>
+ <description>Load Mode Register to Active These bits
+ define the delay between a Load Mode Register command
+ and an Active or Refresh command in number of memory
+ clock cycles. ....</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TXSR</name>
+ <description>Exit Self-refresh delay These bits
+ define the delay from releasing the Self-refresh
+ command to issuing the Activate command in number of
+ memory clock cycles. .... Note: If two SDRAM devices
+ are used, the FMC_SDTR1 and FMC_SDTR2 must be
+ programmed with the same TXSR timing corresponding to
+ the slowest SDRAM device.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TRAS</name>
+ <description>Self refresh time These bits define the
+ minimum Self-refresh period in number of memory clock
+ cycles. ....</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TRC</name>
+ <description>Row cycle delay These bits define the
+ delay between the Refresh command and the Activate
+ command, as well as the delay between two consecutive
+ Refresh commands. It is expressed in number of memory
+ clock cycles. The TRC timing is only configured in
+ the FMC_SDTR1 register. If two SDRAM devices are
+ used, the TRC must be programmed with the timings of
+ the slowest device. .... Note: TRC must match the TRC
+ and TRFC (Auto Refresh period) timings defined in the
+ SDRAM device datasheet. Note: The corresponding bits
+ in the FMC_SDTR2 register are dont
+ care.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TWR</name>
+ <description>Recovery delay These bits define the
+ delay between a Write and a Precharge command in
+ number of memory clock cycles. .... Note: TWR must be
+ programmed to match the write recovery time (tWR)
+ defined in the SDRAM datasheet, and to guarantee
+ that: TWR &amp;#8805; TRAS - TRCD and TWR
+ &amp;#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles,
+ TRCD= 2 cycles. So, TWR &amp;gt;= 2 cycles. TWR must
+ be programmed to 0x1. If two SDRAM devices are used,
+ the FMC_SDTR1 and FMC_SDTR2 must be programmed with
+ the same TWR timing corresponding to the slowest
+ SDRAM device.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TRP</name>
+ <description>Row precharge delay These bits define
+ the delay between a Precharge command and another
+ command in number of memory clock cycles. The TRP
+ timing is only configured in the FMC_SDTR1 register.
+ If two SDRAM devices are used, the TRP must be
+ programmed with the timing of the slowest device.
+ .... Note: The corresponding bits in the FMC_SDTR2
+ register are dont care.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>TRCD</name>
+ <description>Row to column delay These bits define
+ the delay between the Activate command and a
+ Read/Write command in number of memory clock cycles.
+ ....</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_SDCMR</name>
+ <displayName>FMC_SDCMR</displayName>
+ <description>This register contains the command issued
+ when the SDRAM device is accessed. This register is used
+ to initialize the SDRAM device, and to activate the
+ Self-refresh and the Power-down modes. As soon as the
+ MODE field is written, the command will be issued only to
+ one or to both SDRAM banks according to CTB1 and CTB2
+ command bits. This register is the same for both SDRAM
+ banks.</description>
+ <addressOffset>0x150</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MODE</name>
+ <description>Command mode These bits define the
+ command issued to the SDRAM device. Note: When a
+ command is issued, at least one Command Target Bank
+ bit ( CTB1 or CTB2) must be set otherwise the command
+ will be ignored. Note: If two SDRAM banks are used,
+ the Auto-refresh and PALL command must be issued
+ simultaneously to the two devices with CTB1 and CTB2
+ bits set otherwise the command will be ignored. Note:
+ If only one SDRAM bank is used and a command is
+ issued with its associated CTB bit set, the other CTB
+ bit of the unused bank must be kept to
+ 0.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>CTB2</name>
+ <description>Command Target Bank 2 This bit indicates
+ whether the command will be issued to SDRAM Bank 2 or
+ not.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>CTB1</name>
+ <description>Command Target Bank 1 This bit indicates
+ whether the command will be issued to SDRAM Bank 1 or
+ not.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NRFS</name>
+ <description>Number of Auto-refresh These bits define
+ the number of consecutive Auto-refresh commands
+ issued when MODE = 011. ....</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>MRD</name>
+ <description>Mode Register definition This 14-bit
+ field defines the SDRAM Mode Register content. The
+ Mode Register is programmed using the Load Mode
+ Register command. The MRD[13:0] bits are also used to
+ program the extended mode register for mobile
+ SDRAM.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>14</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_SDRTR</name>
+ <displayName>FMC_SDRTR</displayName>
+ <description>This register sets the refresh rate in
+ number of SDCLK clock cycles between the refresh cycles
+ by configuring the Refresh Timer Count value.Examplewhere
+ 64 ms is the SDRAM refresh period.The refresh rate must
+ be increased by 20 SDRAM clock cycles (as in the above
+ example) to obtain a safe margin if an internal refresh
+ request occurs when a read request has been accepted. It
+ corresponds to a COUNT value of 0000111000000 (448). This
+ 13-bit field is loaded into a timer which is decremented
+ using the SDRAM clock. This timer generates a refresh
+ pulse when zero is reached. The COUNT value must be set
+ at least to 41 SDRAM clock cycles.As soon as the
+ FMC_SDRTR register is programmed, the timer starts
+ counting. If the value programmed in the register is 0,
+ no refresh is carried out. This register must not be
+ reprogrammed after the initialization procedure to avoid
+ modifying the refresh rate.Each time a refresh pulse is
+ generated, this 13-bit COUNT field is reloaded into the
+ counter.If a memory access is in progress, the
+ Auto-refresh request is delayed. However, if the memory
+ access and Auto-refresh requests are generated
+ simultaneously, the Auto-refresh takes precedence. If the
+ memory access occurs during a refresh operation, the
+ request is buffered to be processed when the refresh is
+ complete.This register is common to SDRAM bank 1 and bank
+ 2.</description>
+ <addressOffset>0x154</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CRE</name>
+ <description>Clear Refresh error flag This bit is
+ used to clear the Refresh Error Flag (RE) in the
+ Status Register.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>write-only</access>
+ </field>
+ <field>
+ <name>COUNT</name>
+ <description>Refresh Timer Count This 13-bit field
+ defines the refresh rate of the SDRAM device. It is
+ expressed in number of memory clock cycles. It must
+ be set at least to 41 SDRAM clock cycles (0x29).
+ Refresh rate = (COUNT + 1) x SDRAM frequency clock
+ COUNT = (SDRAM refresh period / Number of rows) -
+ 20</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>13</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>REIE</name>
+ <description>RES Interrupt Enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FMC_SDSR</name>
+ <displayName>FMC_SDSR</displayName>
+ <description>SDRAM Status register</description>
+ <addressOffset>0x158</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RE</name>
+ <description>Refresh error flag An interrupt is
+ generated if REIE = 1 and RE = 1</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>MODES1</name>
+ <description>Status Mode for Bank 1 These bits define
+ the Status Mode of SDRAM Bank 1.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODES2</name>
+ <description>Status Mode for Bank 2 These bits define
+ the Status Mode of SDRAM Bank 2.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>CEC</name>
+ <description>CEC</description>
+ <groupName>CEC</groupName>
+ <baseAddress>0x40006C00</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>CEC</name>
+ <description>HDMI-CEC global interrupt</description>
+ <value>94</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CEC_CR</name>
+ <displayName>CEC_CR</displayName>
+ <description>CEC control register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>CECEN</name>
+ <description>CEC Enable The CECEN bit is set and
+ cleared by software. CECEN=1 starts message reception
+ and enables the TXSOM control. CECEN=0 disables the
+ CEC peripheral, clears all bits of CEC_CR register
+ and aborts any on-going reception or
+ transmission.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXSOM</name>
+ <description>Tx Start Of Message TXSOM is set by
+ software to command transmission of the first byte of
+ a CEC message. If the CEC message consists of only
+ one byte, TXEOM must be set before of TXSOM.
+ Start-Bit is effectively started on the CEC line
+ after SFT is counted. If TXSOM is set while a message
+ reception is ongoing, transmission will start after
+ the end of reception. TXSOM is cleared by hardware
+ after the last byte of the message is sent with a
+ positive acknowledge (TXEND=1), in case of
+ transmission underrun (TXUDR=1), negative acknowledge
+ (TXACKE=1), and transmission error (TXERR=1). It is
+ also cleared by CECEN=0. It is not cleared and
+ transmission is automatically retried in case of
+ arbitration lost (ARBLST=1). TXSOM can be also used
+ as a status bit informing application whether any
+ transmission request is pending or under execution.
+ The application can abort a transmission request at
+ any time by clearing the CECEN bit. Note: TXSOM must
+ be set when CECEN=1 TXSOM must be set when
+ transmission data is available into TXDR HEADERs
+ first four bits containing own peripheral address are
+ taken from TXDR[7:4], not from CEC_CFGR.OAR which is
+ used only for reception</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXEOM</name>
+ <description>Tx End Of Message The TXEOM bit is set
+ by software to command transmission of the last byte
+ of a CEC message. TXEOM is cleared by hardware at the
+ same time and under the same conditions as for TXSOM.
+ Note: TXEOM must be set when CECEN=1 TXEOM must be
+ set before writing transmission data to TXDR If TXEOM
+ is set when TXSOM=0, transmitted message will consist
+ of 1 byte (HEADER) only (PING message)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CEC_CFGR</name>
+ <displayName>CEC_CFGR</displayName>
+ <description>This register is used to configure the
+ HDMI-CEC controller. It is mandatory to write CEC_CFGR
+ only when CECEN=0.</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SFT</name>
+ <description>Signal Free Time SFT bits are set by
+ software. In the SFT=0x0 configuration the number of
+ nominal data bit periods waited before transmission
+ is ruled by hardware according to the transmission
+ history. In all the other configurations the SFT
+ number is determined by software. * 0x0 ** 2.5
+ Data-Bit periods if CEC is the last bus initiator
+ with unsuccessful transmission (ARBLST=1, TXERR=1,
+ TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is
+ the new bus initiator ** 6 Data-Bit periods if CEC is
+ the last bus initiator with successful transmission
+ (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2:
+ 1.5 nominal data bit periods * 0x3: 2.5 nominal data
+ bit periods * 0x4: 3.5 nominal data bit periods *
+ 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal
+ data bit periods * 0x7: 6.5 nominal data bit
+ periods</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>RXTOL</name>
+ <description>Rx-Tolerance The RXTOL bit is set and
+ cleared by software. ** Start-Bit, +/- 200 s rise,
+ +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350
+ s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall
+ ** Data-Bit: +/-300 s rise, +/- 500 s
+ fall</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BRESTP</name>
+ <description>Rx-Stop on Bit Rising Error The BRESTP
+ bit is set and cleared by software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BREGEN</name>
+ <description>Generate Error-Bit on Bit Rising Error
+ The BREGEN bit is set and cleared by software. Note:
+ If BRDNOGEN=0, an Error-bit is generated upon BRE
+ detection with BRESTP=1 in broadcast even if
+ BREGEN=0</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LBPEGEN</name>
+ <description>Generate Error-Bit on Long Bit Period
+ Error The LBPEGEN bit is set and cleared by software.
+ Note: If BRDNOGEN=0, an Error-bit is generated upon
+ LBPE detection in broadcast even if
+ LBPEGEN=0</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BRDNOGEN</name>
+ <description>Avoid Error-Bit Generation in Broadcast
+ The BRDNOGEN bit is set and cleared by
+ software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SFTOPT</name>
+ <description>SFT Option Bit The SFTOPT bit is set and
+ cleared by software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OAR</name>
+ <description>Own addresses configuration The OAR bits
+ are set by software to select which destination
+ logical addresses has to be considered in receive
+ mode. Each bit, when set, enables the CEC logical
+ address identified by the given bit position. At the
+ end of HEADER reception, the received destination
+ address is compared with the enabled addresses. In
+ case of matching address, the incoming message is
+ acknowledged and received. In case of non-matching
+ address, the incoming message is received only in
+ listen mode (LSTN=1), but without acknowledge sent.
+ Broadcast messages are always received. Example: OAR
+ = 0b000 0000 0010 0001 means that CEC acknowledges
+ addresses 0x0 and 0x5. Consequently, each message
+ directed to one of these addresses is
+ received.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>15</bitWidth>
+ </field>
+ <field>
+ <name>LSTN</name>
+ <description>Listen mode LSTN bit is set and cleared
+ by software.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CEC_TXDR</name>
+ <displayName>CEC_TXDR</displayName>
+ <description>CEC Tx data register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TXD</name>
+ <description>Tx Data register. TXD is a write-only
+ register containing the data byte to be transmitted.
+ Note: TXD must be written when
+ TXSTART=1</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CEC_RXDR</name>
+ <displayName>CEC_RXDR</displayName>
+ <description>CEC Rx Data Register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RXD</name>
+ <description>Rx Data register. RXD is read-only and
+ contains the last data byte which has been received
+ from the CEC line.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CEC_ISR</name>
+ <displayName>CEC_ISR</displayName>
+ <description>CEC Interrupt and Status
+ Register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RXBR</name>
+ <description>Rx-Byte Received The RXBR bit is set by
+ hardware to inform application that a new byte has
+ been received from the CEC line and stored into the
+ RXD buffer. RXBR is cleared by software write at
+ 1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXEND</name>
+ <description>End Of Reception RXEND is set by
+ hardware to inform application that the last byte of
+ a CEC message is received from the CEC line and
+ stored into the RXD buffer. RXEND is set at the same
+ time of RXBR. RXEND is cleared by software write at
+ 1.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXOVR</name>
+ <description>Rx-Overrun RXOVR is set by hardware if
+ RXBR is not yet cleared at the time a new byte is
+ received on the CEC line and stored into RXD. RXOVR
+ assertion stops message reception so that no
+ acknowledge is sent. In case of broadcast, a negative
+ acknowledge is sent. RXOVR is cleared by software
+ write at 1.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BRE</name>
+ <description>Rx-Bit Rising Error BRE is set by
+ hardware in case a Data-Bit waveform is detected with
+ Bit Rising Error. BRE is set either at the time the
+ misplaced rising edge occurs, or at the end of the
+ maximum BRE tolerance allowed by RXTOL, in case
+ rising edge is still longing. BRE stops message
+ reception if BRESTP=1. BRE generates an Error-Bit on
+ the CEC line if BREGEN=1. BRE is cleared by software
+ write at 1.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SBPE</name>
+ <description>Rx-Short Bit Period Error SBPE is set by
+ hardware in case a Data-Bit waveform is detected with
+ Short Bit Period Error. SBPE is set at the time the
+ anticipated falling edge occurs. SBPE generates an
+ Error-Bit on the CEC line. SBPE is cleared by
+ software write at 1.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LBPE</name>
+ <description>Rx-Long Bit Period Error LBPE is set by
+ hardware in case a Data-Bit waveform is detected with
+ Long Bit Period Error. LBPE is set at the end of the
+ maximum bit-extension tolerance allowed by RXTOL, in
+ case falling edge is still longing. LBPE always stops
+ reception of the CEC message. LBPE generates an
+ Error-Bit on the CEC line if LBPEGEN=1. In case of
+ broadcast, Error-Bit is generated even in case of
+ LBPEGEN=0. LBPE is cleared by software write at
+ 1.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXACKE</name>
+ <description>Rx-Missing Acknowledge In receive mode,
+ RXACKE is set by hardware to inform application that
+ no acknowledge was seen on the CEC line. RXACKE
+ applies only for broadcast messages and in listen
+ mode also for not directly addressed messages
+ (destination address not enabled in OAR). RXACKE
+ aborts message reception. RXACKE is cleared by
+ software write at 1.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARBLST</name>
+ <description>Arbitration Lost ARBLST is set by
+ hardware to inform application that CEC device is
+ switching to reception due to arbitration lost event
+ following the TXSOM command. ARBLST can be due either
+ to a contending CEC device starting earlier or
+ starting at the same time but with higher HEADER
+ priority. After ARBLST assertion TXSOM bit keeps
+ pending for next transmission attempt. ARBLST is
+ cleared by software write at 1.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXBR</name>
+ <description>Tx-Byte Request TXBR is set by hardware
+ to inform application that the next transmission data
+ has to be written to TXDR. TXBR is set when the 4th
+ bit of currently transmitted byte is sent.
+ Application must write the next byte to TXDR within 6
+ nominal data-bit periods before transmission underrun
+ error occurs (TXUDR). TXBR is cleared by software
+ write at 1.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXEND</name>
+ <description>End of Transmission TXEND is set by
+ hardware to inform application that the last byte of
+ the CEC message has been successfully transmitted.
+ TXEND clears the TXSOM and TXEOM control bits. TXEND
+ is cleared by software write at 1.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXUDR</name>
+ <description>Tx-Buffer Underrun In transmission mode,
+ TXUDR is set by hardware if application was not in
+ time to load TXDR before of next byte transmission.
+ TXUDR aborts message transmission and clears TXSOM
+ and TXEOM control bits. TXUDR is cleared by software
+ write at 1</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>Tx-Error In transmission mode, TXERR is
+ set by hardware if the CEC initiator detects low
+ impedance on the CEC line while it is released. TXERR
+ aborts message transmission and clears TXSOM and
+ TXEOM controls. TXERR is cleared by software write at
+ 1.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXACKE</name>
+ <description>Tx-Missing Acknowledge Error In
+ transmission mode, TXACKE is set by hardware to
+ inform application that no acknowledge was received.
+ In case of broadcast transmission, TXACKE informs
+ application that a negative acknowledge was received.
+ TXACKE aborts message transmission and clears TXSOM
+ and TXEOM controls. TXACKE is cleared by software
+ write at 1.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CEC_IER</name>
+ <displayName>CEC_IER</displayName>
+ <description>CEC interrupt enable register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RXBRIE</name>
+ <description>Rx-Byte Received Interrupt Enable The
+ RXBRIE bit is set and cleared by
+ software.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXENDIE</name>
+ <description>End Of Reception Interrupt Enable The
+ RXENDIE bit is set and cleared by
+ software.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXOVRIE</name>
+ <description>Rx-Buffer Overrun Interrupt Enable The
+ RXOVRIE bit is set and cleared by
+ software.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BREIE</name>
+ <description>Bit Rising Error Interrupt Enable The
+ BREIE bit is set and cleared by
+ software.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SBPEIE</name>
+ <description>Short Bit Period Error Interrupt Enable
+ The SBPEIE bit is set and cleared by
+ software.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>LBPEIE</name>
+ <description>Long Bit Period Error Interrupt Enable
+ The LBPEIE bit is set and cleared by
+ software.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXACKIE</name>
+ <description>Rx-Missing Acknowledge Error Interrupt
+ Enable The RXACKIE bit is set and cleared by
+ software.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARBLSTIE</name>
+ <description>Arbitration Lost Interrupt Enable The
+ ARBLSTIE bit is set and cleared by
+ software.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXBRIE</name>
+ <description>Tx-Byte Request Interrupt Enable The
+ TXBRIE bit is set and cleared by
+ software.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXENDIE</name>
+ <description>Tx-End Of Message Interrupt Enable The
+ TXENDIE bit is set and cleared by
+ software.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXUDRIE</name>
+ <description>Tx-Underrun Interrupt Enable The TXUDRIE
+ bit is set and cleared by software.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXERRIE</name>
+ <description>Tx-Error Interrupt Enable The TXERRIE
+ bit is set and cleared by software.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXACKIE</name>
+ <description>Tx-Missing Acknowledge Error Interrupt
+ Enable The TXACKEIE bit is set and cleared by
+ software.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>HSEM</name>
+ <description>HSEM</description>
+ <groupName>HSEM</groupName>
+ <baseAddress>0x58026400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>HSEM0</name>
+ <description>HSEM global interrupt 1</description>
+ <value>125</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>HSEM_R0</name>
+ <displayName>HSEM_R0</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R1</name>
+ <displayName>HSEM_R1</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R2</name>
+ <displayName>HSEM_R2</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R3</name>
+ <displayName>HSEM_R3</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R4</name>
+ <displayName>HSEM_R4</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R5</name>
+ <displayName>HSEM_R5</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R6</name>
+ <displayName>HSEM_R6</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R7</name>
+ <displayName>HSEM_R7</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R8</name>
+ <displayName>HSEM_R8</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R9</name>
+ <displayName>HSEM_R9</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R10</name>
+ <displayName>HSEM_R10</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R11</name>
+ <displayName>HSEM_R11</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x2C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R12</name>
+ <displayName>HSEM_R12</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x30</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R13</name>
+ <displayName>HSEM_R13</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x34</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R14</name>
+ <displayName>HSEM_R14</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x38</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R15</name>
+ <displayName>HSEM_R15</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x3C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R16</name>
+ <displayName>HSEM_R16</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x40</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R17</name>
+ <displayName>HSEM_R17</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x44</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R18</name>
+ <displayName>HSEM_R18</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x48</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R19</name>
+ <displayName>HSEM_R19</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x4C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R20</name>
+ <displayName>HSEM_R20</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x50</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R21</name>
+ <displayName>HSEM_R21</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x54</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R22</name>
+ <displayName>HSEM_R22</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x58</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R23</name>
+ <displayName>HSEM_R23</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x5C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R24</name>
+ <displayName>HSEM_R24</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x60</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R25</name>
+ <displayName>HSEM_R25</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x64</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R26</name>
+ <displayName>HSEM_R26</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x68</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R27</name>
+ <displayName>HSEM_R27</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x6C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R28</name>
+ <displayName>HSEM_R28</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x70</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R29</name>
+ <displayName>HSEM_R29</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x74</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R30</name>
+ <displayName>HSEM_R30</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x78</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_R31</name>
+ <displayName>HSEM_R31</displayName>
+ <description>HSEM register HSEM_R0 HSEM_R31</description>
+ <addressOffset>0x7C</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR0</name>
+ <displayName>HSEM_RLR0</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0x80</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR1</name>
+ <displayName>HSEM_RLR1</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0x84</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR2</name>
+ <displayName>HSEM_RLR2</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0x88</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR3</name>
+ <displayName>HSEM_RLR3</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0x8C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR4</name>
+ <displayName>HSEM_RLR4</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0x90</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR5</name>
+ <displayName>HSEM_RLR5</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0x94</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR6</name>
+ <displayName>HSEM_RLR6</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0x98</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR7</name>
+ <displayName>HSEM_RLR7</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0x9C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR8</name>
+ <displayName>HSEM_RLR8</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xA0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR9</name>
+ <displayName>HSEM_RLR9</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xA4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR10</name>
+ <displayName>HSEM_RLR10</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xA8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR11</name>
+ <displayName>HSEM_RLR11</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xAC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR12</name>
+ <displayName>HSEM_RLR12</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xB0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR13</name>
+ <displayName>HSEM_RLR13</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xB4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR14</name>
+ <displayName>HSEM_RLR14</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xB8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR15</name>
+ <displayName>HSEM_RLR15</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xBC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR16</name>
+ <displayName>HSEM_RLR16</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xC0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR17</name>
+ <displayName>HSEM_RLR17</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xC4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR18</name>
+ <displayName>HSEM_RLR18</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xC8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR19</name>
+ <displayName>HSEM_RLR19</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xCC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR20</name>
+ <displayName>HSEM_RLR20</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xD0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR21</name>
+ <displayName>HSEM_RLR21</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xD4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR22</name>
+ <displayName>HSEM_RLR22</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xD8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR23</name>
+ <displayName>HSEM_RLR23</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xDC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR24</name>
+ <displayName>HSEM_RLR24</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xE0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR25</name>
+ <displayName>HSEM_RLR25</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xE4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR26</name>
+ <displayName>HSEM_RLR26</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xE8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR27</name>
+ <displayName>HSEM_RLR27</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xEC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR28</name>
+ <displayName>HSEM_RLR28</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xF0</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR29</name>
+ <displayName>HSEM_RLR29</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xF4</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR30</name>
+ <displayName>HSEM_RLR30</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xF8</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_RLR31</name>
+ <displayName>HSEM_RLR31</displayName>
+ <description>HSEM Read lock register</description>
+ <addressOffset>0xFC</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PROCID</name>
+ <description>Semaphore ProcessID</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>MASTERID</name>
+ <description>Semaphore MasterID</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>Lock indication</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_IER</name>
+ <displayName>HSEM_IER</displayName>
+ <description>HSEM Interrupt enable register</description>
+ <addressOffset>0x100</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ISEM0</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM1</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM2</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM3</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM4</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM5</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM6</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM7</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM8</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM9</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM10</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM11</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM12</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM13</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM14</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM15</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM16</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM17</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM18</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM19</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM20</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM21</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM22</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM23</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM24</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM25</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM26</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM27</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM28</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM29</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM30</name>
+ <description>Interrupt semaphore n enable
+ bit</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM31</name>
+ <description>Interrupt(N) semaphore n enable
+ bit.</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_ICR</name>
+ <displayName>HSEM_ICR</displayName>
+ <description>HSEM Interrupt clear register</description>
+ <addressOffset>0x104</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ISEM0</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM1</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM2</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM3</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM4</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM5</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM6</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM7</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM8</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM9</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM10</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM11</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM12</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM13</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM14</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM15</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM16</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM17</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM18</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM19</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM20</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM21</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM22</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM23</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM24</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM25</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM26</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM27</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM28</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM29</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM30</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM31</name>
+ <description>Interrupt(N) semaphore n clear
+ bit</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_ISR</name>
+ <displayName>HSEM_ISR</displayName>
+ <description>HSEM Interrupt status register</description>
+ <addressOffset>0x108</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ISEM0</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM1</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM2</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM3</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM4</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM5</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM6</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM7</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM8</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM9</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM10</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM11</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM12</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM13</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM14</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM15</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM16</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM17</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM18</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM19</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM20</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM21</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM22</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM23</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM24</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM25</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM26</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM27</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM28</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM29</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM30</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM31</name>
+ <description>Interrupt(N) semaphore n status bit
+ before enable (mask)</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_MISR</name>
+ <displayName>HSEM_MISR</displayName>
+ <description>HSEM Masked interrupt status
+ register</description>
+ <addressOffset>0x10C</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ISEM0</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM1</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM2</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM3</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM4</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM5</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM6</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM7</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM8</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM9</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM10</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM11</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM12</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM13</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM14</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM15</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM16</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM17</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM18</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM19</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM20</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM21</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM22</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM23</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM24</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM25</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM26</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM27</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>27</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM28</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM29</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM30</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ISEM31</name>
+ <description>masked interrupt(N) semaphore n status
+ bit after enable (mask)</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_CR</name>
+ <displayName>HSEM_CR</displayName>
+ <description>HSEM Clear register</description>
+ <addressOffset>0x140</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>MASTERID</name>
+ <description>MasterID of semaphores to be
+ cleared</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>KEY</name>
+ <description>Semaphore clear Key</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HSEM_KEYR</name>
+ <displayName>HSEM_KEYR</displayName>
+ <description>HSEM Interrupt clear register</description>
+ <addressOffset>0x144</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>KEY</name>
+ <description>Semaphore Clear Key</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>I2C1</name>
+ <description>I2C</description>
+ <groupName>I2C</groupName>
+ <baseAddress>0x40005400</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>I2C1_EV</name>
+ <description>I2C1 event interrupt</description>
+ <value>31</value>
+ </interrupt>
+ <interrupt>
+ <name>I2C1_ER</name>
+ <description>I2C1 error interrupt</description>
+ <value>32</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>I2C_CR1</name>
+ <displayName>I2C_CR1</displayName>
+ <description>Access: No wait states, except if a write
+ access occurs while a write access to this register is
+ ongoing. In this case, wait states are inserted in the
+ second write access until the previous one is completed.
+ The latency of the second write access can be up to 2 x
+ PCLK1 + 6 x I2CCLK.</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PE</name>
+ <description>Peripheral enable Note: When PE=0, the
+ I2C SCL and SDA lines are released. Internal state
+ machines and status bits are put back to their reset
+ value. When cleared, PE must be kept low for at least
+ 3 APB clock cycles.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXIE</name>
+ <description>TX Interrupt enable</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXIE</name>
+ <description>RX Interrupt enable</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADDRIE</name>
+ <description>Address match Interrupt enable (slave
+ only)</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NACKIE</name>
+ <description>Not acknowledge received Interrupt
+ enable</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STOPIE</name>
+ <description>STOP detection Interrupt
+ enable</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TCIE</name>
+ <description>Transfer Complete interrupt enable Note:
+ Any of these events will generate an interrupt:
+ Transfer Complete (TC) Transfer Complete Reload
+ (TCR)</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ERRIE</name>
+ <description>Error interrupts enable Note: Any of
+ these errors generate an interrupt: Arbitration Loss
+ (ARLO) Bus Error detection (BERR) Overrun/Underrun
+ (OVR) Timeout detection (TIMEOUT) PEC error detection
+ (PECERR) Alert pin event detection
+ (ALERT)</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>DNF</name>
+ <description>Digital noise filter These bits are used
+ to configure the digital noise filter on SDA and SCL
+ input. The digital filter will filter spikes with a
+ length of up to DNF[3:0] * tI2CCLK ... Note: If the
+ analog filter is also enabled, the digital filter is
+ added to the analog filter. This filter can only be
+ programmed when the I2C is disabled (PE =
+ 0).</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>ANFOFF</name>
+ <description>Analog noise filter OFF Note: This bit
+ can only be programmed when the I2C is disabled (PE =
+ 0).</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TXDMAEN</name>
+ <description>DMA transmission requests
+ enable</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXDMAEN</name>
+ <description>DMA reception requests
+ enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SBC</name>
+ <description>Slave byte control This bit is used to
+ enable hardware byte control in slave
+ mode.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NOSTRETCH</name>
+ <description>Clock stretching disable This bit is
+ used to disable clock stretching in slave mode. It
+ must be kept cleared in master mode. Note: This bit
+ can only be programmed when the I2C is disabled (PE =
+ 0).</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>WUPEN</name>
+ <description>Wakeup from Stop mode enable Note: If
+ the Wakeup from Stop mode feature is not supported,
+ this bit is reserved and forced by hardware to 0.
+ Please refer to Section25.3: I2C implementation.
+ Note: WUPEN can be set only when DNF =
+ 0000</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>GCEN</name>
+ <description>General call enable</description>
+ <bitOffset>19</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMBHEN</name>
+ <description>SMBus Host address enable Note: If the
+ SMBus feature is not supported, this bit is reserved
+ and forced by hardware to 0. Please refer to
+ Section25.3: I2C implementation.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SMBDEN</name>
+ <description>SMBus Device Default address enable
+ Note: If the SMBus feature is not supported, this bit
+ is reserved and forced by hardware to 0. Please refer
+ to Section25.3: I2C implementation.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALERTEN</name>
+ <description>SMBus alert enable Device mode
+ (SMBHEN=0): Host mode (SMBHEN=1): Note: When
+ ALERTEN=0, the SMBA pin can be used as a standard
+ GPIO. If the SMBus feature is not supported, this bit
+ is reserved and forced by hardware to 0. Please refer
+ to Section25.3: I2C implementation.</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PECEN</name>
+ <description>PEC enable Note: If the SMBus feature is
+ not supported, this bit is reserved and forced by
+ hardware to 0. Please refer to Section25.3: I2C
+ implementation.</description>
+ <bitOffset>23</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_CR2</name>
+ <displayName>I2C_CR2</displayName>
+ <description>Access: No wait states, except if a write
+ access occurs while a write access to this register is
+ ongoing. In this case, wait states are inserted in the
+ second write access until the previous one is completed.
+ The latency of the second write access can be up to 2 x
+ PCLK1 + 6 x I2CCLK.</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SADD0</name>
+ <description>Slave address bit 0 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): This bit is dont
+ care In 10-bit addressing mode (ADD10 = 1): This bit
+ should be written with bit 0 of the slave address to
+ be sent Note: Changing these bits when the START bit
+ is set is not allowed.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD1</name>
+ <description>Slave address bit 7:1 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits should
+ be written with the 7-bit slave address to be sent In
+ 10-bit addressing mode (ADD10 = 1): These bits should
+ be written with bits 7:1 of the slave address to be
+ sent. Note: Changing these bits when the START bit is
+ set is not allowed.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD2</name>
+ <description>Slave address bit 7:1 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits should
+ be written with the 7-bit slave address to be sent In
+ 10-bit addressing mode (ADD10 = 1): These bits should
+ be written with bits 7:1 of the slave address to be
+ sent. Note: Changing these bits when the START bit is
+ set is not allowed.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD3</name>
+ <description>Slave address bit 7:1 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits should
+ be written with the 7-bit slave address to be sent In
+ 10-bit addressing mode (ADD10 = 1): These bits should
+ be written with bits 7:1 of the slave address to be
+ sent. Note: Changing these bits when the START bit is
+ set is not allowed.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD4</name>
+ <description>Slave address bit 7:1 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits should
+ be written with the 7-bit slave address to be sent In
+ 10-bit addressing mode (ADD10 = 1): These bits should
+ be written with bits 7:1 of the slave address to be
+ sent. Note: Changing these bits when the START bit is
+ set is not allowed.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD5</name>
+ <description>Slave address bit 7:1 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits should
+ be written with the 7-bit slave address to be sent In
+ 10-bit addressing mode (ADD10 = 1): These bits should
+ be written with bits 7:1 of the slave address to be
+ sent. Note: Changing these bits when the START bit is
+ set is not allowed.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD6</name>
+ <description>Slave address bit 7:1 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits should
+ be written with the 7-bit slave address to be sent In
+ 10-bit addressing mode (ADD10 = 1): These bits should
+ be written with bits 7:1 of the slave address to be
+ sent. Note: Changing these bits when the START bit is
+ set is not allowed.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD7</name>
+ <description>Slave address bit 7:1 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits should
+ be written with the 7-bit slave address to be sent In
+ 10-bit addressing mode (ADD10 = 1): These bits should
+ be written with bits 7:1 of the slave address to be
+ sent. Note: Changing these bits when the START bit is
+ set is not allowed.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD8</name>
+ <description>Slave address bit 9:8 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits are
+ dont care In 10-bit addressing mode (ADD10 = 1):
+ These bits should be written with bits 9:8 of the
+ slave address to be sent Note: Changing these bits
+ when the START bit is set is not
+ allowed.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>SADD9</name>
+ <description>Slave address bit 9:8 (master mode) In
+ 7-bit addressing mode (ADD10 = 0): These bits are
+ dont care In 10-bit addressing mode (ADD10 = 1):
+ These bits should be written with bits 9:8 of the
+ slave address to be sent Note: Changing these bits
+ when the START bit is set is not
+ allowed.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RD_WRN</name>
+ <description>Transfer direction (master mode) Note:
+ Changing this bit when the START bit is set is not
+ allowed.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ADD10</name>
+ <description>10-bit addressing mode (master mode)
+ Note: Changing this bit when the START bit is set is
+ not allowed.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>HEAD10R</name>
+ <description>10-bit address header only read
+ direction (master receiver mode) Note: Changing this
+ bit when the START bit is set is not
+ allowed.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>START</name>
+ <description>Start generation This bit is set by
+ software, and cleared by hardware after the Start
+ followed by the address sequence is sent, by an
+ arbitration loss, by a timeout error detection, or
+ when PE = 0. It can also be cleared by software by
+ writing 1 to the ADDRCF bit in the I2C_ICR register.
+ If the I2C is already in master mode with AUTOEND =
+ 0, setting this bit generates a Repeated Start
+ condition when RELOAD=0, after the end of the NBYTES
+ transfer. Otherwise setting this bit will generate a
+ START condition once the bus is free. Note: Writing 0
+ to this bit has no effect. The START bit can be set
+ even if the bus is BUSY or I2C is in slave mode. This
+ bit has no effect when RELOAD is set.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STOP</name>
+ <description>Stop generation (master mode) The bit is
+ set by software, cleared by hardware when a Stop
+ condition is detected, or when PE = 0. In Master
+ Mode: Note: Writing 0 to this bit has no
+ effect.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NACK</name>
+ <description>NACK generation (slave mode) The bit is
+ set by software, cleared by hardware when the NACK is
+ sent, or when a STOP condition or an Address matched
+ is received, or when PE=0. Note: Writing 0 to this
+ bit has no effect. This bit is used in slave mode
+ only: in master receiver mode, NACK is automatically
+ generated after last byte preceding STOP or RESTART
+ condition, whatever the NACK bit value. When an
+ overrun occurs in slave receiver NOSTRETCH mode, a
+ NACK is automatically generated whatever the NACK bit
+ value. When hardware PEC checking is enabled
+ (PECBYTE=1), the PEC acknowledge value does not
+ depend on the NACK value.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NBYTES</name>
+ <description>Number of bytes The number of bytes to
+ be transmitted/received is programmed there. This
+ field is dont care in slave mode with SBC=0. Note:
+ Changing these bits when the START bit is set is not
+ allowed.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>RELOAD</name>
+ <description>NBYTES reload mode This bit is set and
+ cleared by software.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AUTOEND</name>
+ <description>Automatic end mode (master mode) This
+ bit is set and cleared by software. Note: This bit
+ has no effect in slave mode or when the RELOAD bit is
+ set.</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PECBYTE</name>
+ <description>Packet error checking byte This bit is
+ set by software, and cleared by hardware when the PEC
+ is transferred, or when a STOP condition or an
+ Address matched is received, also when PE=0. Note:
+ Writing 0 to this bit has no effect. This bit has no
+ effect when RELOAD is set. This bit has no effect is
+ slave mode when SBC=0. If the SMBus feature is not
+ supported, this bit is reserved and forced by
+ hardware to 0. Please refer to Section25.3: I2C
+ implementation.</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_OAR1</name>
+ <displayName>I2C_OAR1</displayName>
+ <description>Access: No wait states, except if a write
+ access occurs while a write access to this register is
+ ongoing. In this case, wait states are inserted in the
+ second write access until the previous one is completed.
+ The latency of the second write access can be up to 2 x
+ PCLK1 + 6 x I2CCLK.</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OA1</name>
+ <description>Interface address 7-bit addressing mode:
+ dont care 10-bit addressing mode: bits 9:8 of address
+ Note: These bits can be written only when OA1EN=0.
+ OA1[7:1]: Interface address Bits 7:1 of address Note:
+ These bits can be written only when OA1EN=0. OA1[0]:
+ Interface address 7-bit addressing mode: dont care
+ 10-bit addressing mode: bit 0 of address Note: This
+ bit can be written only when OA1EN=0.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>10</bitWidth>
+ </field>
+ <field>
+ <name>OA1MODE</name>
+ <description>Own Address 1 10-bit mode Note: This bit
+ can be written only when OA1EN=0.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OA1EN</name>
+ <description>Own Address 1 enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_OAR2</name>
+ <displayName>I2C_OAR2</displayName>
+ <description>Access: No wait states, except if a write
+ access occurs while a write access to this register is
+ ongoing. In this case, wait states are inserted in the
+ second write access until the previous one is completed.
+ The latency of the second write access can be up to 2 x
+ PCLK1 + 6 x I2CCLK.</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OA2</name>
+ <description>Interface address bits 7:1 of address
+ Note: These bits can be written only when
+ OA2EN=0.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>7</bitWidth>
+ </field>
+ <field>
+ <name>OA2MSK</name>
+ <description>Own Address 2 masks Note: These bits can
+ be written only when OA2EN=0. As soon as OA2MSK is
+ not equal to 0, the reserved I2C addresses (0b0000xxx
+ and 0b1111xxx) are not acknowledged even if the
+ comparison matches.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>3</bitWidth>
+ </field>
+ <field>
+ <name>OA2EN</name>
+ <description>Own Address 2 enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_TIMINGR</name>
+ <displayName>I2C_TIMINGR</displayName>
+ <description>Access: No wait states</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>SCLL</name>
+ <description>SCL low period (master mode) This field
+ is used to generate the SCL low period in master
+ mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also
+ used to generate tBUF and tSU:STA
+ timings.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SCLH</name>
+ <description>SCL high period (master mode) This field
+ is used to generate the SCL high period in master
+ mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also
+ used to generate tSU:STO and tHD:STA
+ timing.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>SDADEL</name>
+ <description>Data hold time This field is used to
+ generate the delay tSDADEL between SCL falling edge
+ and SDA edge. In master mode and in slave mode with
+ NOSTRETCH = 0, the SCL line is stretched low during
+ tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is
+ used to generate tHD:DAT timing.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>SCLDEL</name>
+ <description>Data setup time This field is used to
+ generate a delay tSCLDEL between SDA edge and SCL
+ rising edge. In master mode and in slave mode with
+ NOSTRETCH = 0, the SCL line is stretched low during
+ tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL
+ is used to generate tSU:DAT timing.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>PRESC</name>
+ <description>Timing prescaler This field is used to
+ prescale I2CCLK in order to generate the clock period
+ tPRESC used for data setup and hold counters (refer
+ to I2C timings on page9) and for SCL high and low
+ level counters (refer to I2C master initialization on
+ page24). tPRESC = (PRESC+1) x tI2CCLK</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_TIMEOUTR</name>
+ <displayName>I2C_TIMEOUTR</displayName>
+ <description>Access: No wait states, except if a write
+ access occurs while a write access to this register is
+ ongoing. In this case, wait states are inserted in the
+ second write access until the previous one is completed.
+ The latency of the second write access can be up to 2 x
+ PCLK1 + 6 x I2CCLK.</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TIMEOUTA</name>
+ <description>Bus Timeout A This field is used to
+ configure: The SCL low timeout condition tTIMEOUT
+ when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK
+ The bus idle condition (both SCL and SDA high) when
+ TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These
+ bits can be written only when
+ TIMOUTEN=0.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>TIDLE</name>
+ <description>Idle clock timeout detection Note: This
+ bit can be written only when
+ TIMOUTEN=0.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIMOUTEN</name>
+ <description>Clock timeout enable</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIMEOUTB</name>
+ <description>Bus timeout B This field is used to
+ configure the cumulative clock extension timeout: In
+ master mode, the master cumulative clock low extend
+ time (tLOW:MEXT) is detected In slave mode, the slave
+ cumulative clock low extend time (tLOW:SEXT) is
+ detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK
+ Note: These bits can be written only when
+ TEXTEN=0.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>12</bitWidth>
+ </field>
+ <field>
+ <name>TEXTEN</name>
+ <description>Extended clock timeout
+ enable</description>
+ <bitOffset>31</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_ISR</name>
+ <displayName>I2C_ISR</displayName>
+ <description>Access: No wait states</description>
+ <addressOffset>0x18</addressOffset>
+ <size>0x20</size>
+ <resetValue>0x00000001</resetValue>
+ <fields>
+ <field>
+ <name>TXE</name>
+ <description>Transmit data register empty
+ (transmitters) This bit is set by hardware when the
+ I2C_TXDR register is empty. It is cleared when the
+ next data to be sent is written in the I2C_TXDR
+ register. This bit can be written to 1 by software in
+ order to flush the transmit data register I2C_TXDR.
+ Note: This bit is set by hardware when
+ PE=0.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>TXIS</name>
+ <description>Transmit interrupt status (transmitters)
+ This bit is set by hardware when the I2C_TXDR
+ register is empty and the data to be transmitted must
+ be written in the I2C_TXDR register. It is cleared
+ when the next data to be sent is written in the
+ I2C_TXDR register. This bit can be written to 1 by
+ software when NOSTRETCH=1 only, in order to generate
+ a TXIS event (interrupt if TXIE=1 or DMA request if
+ TXDMAEN=1). Note: This bit is cleared by hardware
+ when PE=0.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>RXNE</name>
+ <description>Receive data register not empty
+ (receivers) This bit is set by hardware when the
+ received data is copied into the I2C_RXDR register,
+ and is ready to be read. It is cleared when I2C_RXDR
+ is read. Note: This bit is cleared by hardware when
+ PE=0.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ADDR</name>
+ <description>Address matched (slave mode) This bit is
+ set by hardware as soon as the received slave address
+ matched with one of the enabled slave addresses. It
+ is cleared by software by setting ADDRCF bit. Note:
+ This bit is cleared by hardware when
+ PE=0.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>NACKF</name>
+ <description>Not Acknowledge received flag This flag
+ is set by hardware when a NACK is received after a
+ byte transmission. It is cleared by software by
+ setting the NACKCF bit. Note: This bit is cleared by
+ hardware when PE=0.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>STOPF</name>
+ <description>Stop detection flag This flag is set by
+ hardware when a Stop condition is detected on the bus
+ and the peripheral is involved in this transfer:
+ either as a master, provided that the STOP condition
+ is generated by the peripheral. or as a slave,
+ provided that the peripheral has been addressed
+ previously during this transfer. It is cleared by
+ software by setting the STOPCF bit. Note: This bit is
+ cleared by hardware when PE=0.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TC</name>
+ <description>Transfer Complete (master mode) This
+ flag is set by hardware when RELOAD=0, AUTOEND=0 and
+ NBYTES data have been transferred. It is cleared by
+ software when START bit or STOP bit is set. Note:
+ This bit is cleared by hardware when
+ PE=0.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TCR</name>
+ <description>Transfer Complete Reload This flag is
+ set by hardware when RELOAD=1 and NBYTES data have
+ been transferred. It is cleared by software when
+ NBYTES is written to a non-zero value. Note: This bit
+ is cleared by hardware when PE=0. This flag is only
+ for master mode, or for slave mode when the SBC bit
+ is set.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BERR</name>
+ <description>Bus error This flag is set by hardware
+ when a misplaced Start or Stop condition is detected
+ whereas the peripheral is involved in the transfer.
+ The flag is not set during the address phase in slave
+ mode. It is cleared by software by setting BERRCF
+ bit. Note: This bit is cleared by hardware when
+ PE=0.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ARLO</name>
+ <description>Arbitration lost This flag is set by
+ hardware in case of arbitration loss. It is cleared
+ by software by setting the ARLOCF bit. Note: This bit
+ is cleared by hardware when PE=0.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>OVR</name>
+ <description>Overrun/Underrun (slave mode) This flag
+ is set by hardware in slave mode with NOSTRETCH=1,
+ when an overrun/underrun error occurs. It is cleared
+ by software by setting the OVRCF bit. Note: This bit
+ is cleared by hardware when PE=0.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PECERR</name>
+ <description>PEC Error in reception This flag is set
+ by hardware when the received PEC does not match with
+ the PEC register content. A NACK is automatically
+ sent after the wrong PEC reception. It is cleared by
+ software by setting the PECCF bit. Note: This bit is
+ cleared by hardware when PE=0. If the SMBus feature
+ is not supported, this bit is reserved and forced by
+ hardware to 0. Please refer to Section25.3: I2C
+ implementation.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>TIMEOUT</name>
+ <description>Timeout or tLOW detection flag This flag
+ is set by hardware when a timeout or extended clock
+ timeout occurred. It is cleared by software by
+ setting the TIMEOUTCF bit. Note: This bit is cleared
+ by hardware when PE=0. If the SMBus feature is not
+ supported, this bit is reserved and forced by
+ hardware to 0. Please refer to Section25.3: I2C
+ implementation.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ALERT</name>
+ <description>SMBus alert This flag is set by hardware
+ when SMBHEN=1 (SMBus host configuration), ALERTEN=1
+ and a SMBALERT event (falling edge) is detected on
+ SMBA pin. It is cleared by software by setting the
+ ALERTCF bit. Note: This bit is cleared by hardware
+ when PE=0. If the SMBus feature is not supported,
+ this bit is reserved and forced by hardware to 0.
+ Please refer to Section25.3: I2C
+ implementation.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>BUSY</name>
+ <description>Bus busy This flag indicates that a
+ communication is in progress on the bus. It is set by
+ hardware when a START condition is detected. It is
+ cleared by hardware when a Stop condition is
+ detected, or when PE=0.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>DIR</name>
+ <description>Transfer direction (Slave mode) This
+ flag is updated when an address match event occurs
+ (ADDR=1).</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>ADDCODE</name>
+ <description>Address match code (Slave mode) These
+ bits are updated with the received address when an
+ address match event occurs (ADDR = 1). In the case of
+ a 10-bit address, ADDCODE provides the 10-bit header
+ followed by the 2 MSBs of the address.</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>7</bitWidth>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_ICR</name>
+ <displayName>I2C_ICR</displayName>
+ <description>Access: No wait states</description>
+ <addressOffset>0x1C</addressOffset>
+ <size>0x20</size>
+ <access>write-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ADDRCF</name>
+ <description>Address matched flag clear Writing 1 to
+ this bit clears the ADDR flag in the I2C_ISR
+ register. Writing 1 to this bit also clears the START
+ bit in the I2C_CR2 register.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>NACKCF</name>
+ <description>Not Acknowledge flag clear Writing 1 to
+ this bit clears the ACKF flag in I2C_ISR
+ register.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>STOPCF</name>
+ <description>Stop detection flag clear Writing 1 to
+ this bit clears the STOPF flag in the I2C_ISR
+ register.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>BERRCF</name>
+ <description>Bus error flag clear Writing 1 to this
+ bit clears the BERRF flag in the I2C_ISR
+ register.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ARLOCF</name>
+ <description>Arbitration Lost flag clear Writing 1 to
+ this bit clears the ARLO flag in the I2C_ISR
+ register.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OVRCF</name>
+ <description>Overrun/Underrun flag clear Writing 1 to
+ this bit clears the OVR flag in the I2C_ISR
+ register.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PECCF</name>
+ <description>PEC Error flag clear Writing 1 to this
+ bit clears the PECERR flag in the I2C_ISR register.
+ Note: If the SMBus feature is not supported, this bit
+ is reserved and forced by hardware to 0. Please refer
+ to Section25.3: I2C implementation.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>TIMOUTCF</name>
+ <description>Timeout detection flag clear Writing 1
+ to this bit clears the TIMEOUT flag in the I2C_ISR
+ register. Note: If the SMBus feature is not
+ supported, this bit is reserved and forced by
+ hardware to 0. Please refer to Section25.3: I2C
+ implementation.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ALERTCF</name>
+ <description>Alert flag clear Writing 1 to this bit
+ clears the ALERT flag in the I2C_ISR register. Note:
+ If the SMBus feature is not supported, this bit is
+ reserved and forced by hardware to 0. Please refer to
+ Section25.3: I2C implementation.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_PECR</name>
+ <displayName>I2C_PECR</displayName>
+ <description>Access: No wait states</description>
+ <addressOffset>0x20</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>PEC</name>
+ <description>Packet error checking register This
+ field contains the internal PEC when PECEN=1. The PEC
+ is cleared by hardware when PE=0.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_RXDR</name>
+ <displayName>I2C_RXDR</displayName>
+ <description>Access: No wait states</description>
+ <addressOffset>0x24</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>RXDATA</name>
+ <description>8-bit receive data Data byte received
+ from the I2C bus.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_TXDR</name>
+ <displayName>I2C_TXDR</displayName>
+ <description>Access: No wait states</description>
+ <addressOffset>0x28</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>TXDATA</name>
+ <description>8-bit transmit data Data byte to be
+ transmitted to the I2C bus. Note: These bits can be
+ written only when TXE=1.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="I2C1">
+ <name>I2C2</name>
+ <baseAddress>0x40005800</baseAddress>
+ <interrupt>
+ <name>I2C2_EV</name>
+ <description>I2C2 event interrupt</description>
+ <value>33</value>
+ </interrupt>
+ <interrupt>
+ <name>I2C2_ER</name>
+ <description>I2C2 error interrupt</description>
+ <value>34</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="I2C1">
+ <name>I2C3</name>
+ <baseAddress>0x40005C00</baseAddress>
+ <interrupt>
+ <name>I2C3_EV</name>
+ <description>I2C3 event interrupt</description>
+ <value>72</value>
+ </interrupt>
+ <interrupt>
+ <name>I2C3_ER</name>
+ <description>I2C3 error interrupt</description>
+ <value>73</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="I2C1">
+ <name>I2C4</name>
+ <baseAddress>0x58001C00</baseAddress>
+ <interrupt>
+ <name>I2C4_EV</name>
+ <description>I2C4 event interrupt</description>
+ <value>95</value>
+ </interrupt>
+ <interrupt>
+ <name>I2C4_ER</name>
+ <description>I2C4 error interrupt</description>
+ <value>96</value>
+ </interrupt>
+ </peripheral>
+ <peripheral>
+ <name>GPIOA</name>
+ <description>GPIO</description>
+ <groupName>GPIO</groupName>
+ <baseAddress>0x58020000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>GPIOA_MODER</name>
+ <displayName>GPIOA_MODER</displayName>
+ <description>GPIO port mode register</description>
+ <addressOffset>0x0</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0xABFFFFFF</resetValue>
+ <fields>
+ <field>
+ <name>MODE0</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE1</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE2</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE3</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE4</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE5</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE6</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE7</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE8</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE9</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE10</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE11</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE12</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE13</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE14</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>MODE15</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O mode.</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>GPIOA_OTYPER</name>
+ <displayName>GPIOA_OTYPER</displayName>
+ <description>GPIO port output type register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OT0</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT1</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT2</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT3</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT4</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT5</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT6</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT7</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT8</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT9</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT10</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT11</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT12</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT13</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT14</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>OT15</name>
+ <description>Port x configuration bits (y = 0..15)
+ These bits are written by software to configure the
+ I/O output type.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>GPIOA_OSPEEDR</name>
+ <displayName>GPIOA_OSPEEDR</displayName>
+ <description>GPIO port output speed
+ register</description>
+ <addressOffset>0x8</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x0C000000</resetValue>
+ <fields>
+ <field>
+ <name>OSPEED0</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED1</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED2</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED3</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED4</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED5</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED6</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED7</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED8</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED9</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED10</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED11</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED12</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED13</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED14</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>OSPEED15</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O output speed. Note: Refer to the
+ device datasheet for the frequency specifications and
+ the power supply and load conditions for each
+ speed.</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>GPIOA_PUPDR</name>
+ <displayName>GPIOA_PUPDR</displayName>
+ <description>GPIO port pull-up/pull-down
+ register</description>
+ <addressOffset>0xC</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x12100000</resetValue>
+ <fields>
+ <field>
+ <name>PUPD0</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD1</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD2</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD3</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD4</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD5</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD6</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD7</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD8</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD9</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>18</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD10</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD11</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD12</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>24</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD13</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>26</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD14</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ <field>
+ <name>PUPD15</name>
+ <description>[1:0]: Port x configuration bits (y =
+ 0..15) These bits are written by software to
+ configure the I/O pull-up or pull-down</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>2</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>GPIOA_IDR</name>
+ <displayName>GPIOA_IDR</displayName>
+ <description>GPIO port input data register</description>
+ <addressOffset>0x10</addressOffset>
+ <size>0x20</size>
+ <access>read-only</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>ID0</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID1</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID2</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID3</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID4</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID5</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID6</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID7</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID8</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID9</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID10</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID11</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID12</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>12</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID13</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>13</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID14</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>14</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>ID15</name>
+ <description>Port input data bit (y = 0..15) These
+ bits are read-only. They contain the input value of
+ the corresponding I/O port.</description>
+ <bitOffset>15</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>GPIOA_ODR</name>
+ <displayName>GPIOA_ODR</displayName>
+ <description>GPIO port output data register</description>
+ <addressOffset>0x14</addressOffset>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <fields>
+ <field>
+ <name>OD0</name>
+ <description>Port output data bit These bits can be